-
2
-
-
33846098642
-
Design and performance modeling for single-wall carbon nanotubes as local, semi-global and global interconnects in gigascale integrated systems
-
Jan.
-
A. Naeemi and J. D. Meindl, "Design and performance modeling for single-wall carbon nanotubes as local, semi-global and global interconnects in gigascale integrated systems," IEEE Trans. Electron Devices, vol. 54, no. 1, pp. 26-37, Jan. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.1
, pp. 26-37
-
-
Naeemi, A.1
Meindl, J.D.2
-
3
-
-
36849005415
-
Performance comparisons between carbon nanotubes, optical, and Cu for future highperformance on-chip interconnect applications
-
Dec.
-
K. H. Koo, H. Cho, P. Kapur, and K. C. Saraswat, "Performance comparisons between carbon nanotubes, optical, and Cu for future highperformance on-chip interconnect applications," IEEE Trans. Electron Devices, vol. 54, no. 12, pp. 3206-3215, Dec. 2007.
-
(2007)
IEEE Trans. Electron Devices
, vol.54
, Issue.12
, pp. 3206-3215
-
-
Koo, K.H.1
Cho, H.2
Kapur, P.3
Saraswat, K.C.4
-
4
-
-
33947642463
-
Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques
-
Oct.
-
A. Nieuwoudt and Y. Massoud, "Evaluating the impact of resistance in carbon nanotube bundles for VLSI interconnect using diameter-dependent modeling techniques," IEEE Trans. Electron Devices, vol. 53, no. 10, pp. 2460-2466, Oct. 2006.
-
(2006)
IEEE Trans. Electron Devices
, vol.53
, Issue.10
, pp. 2460-2466
-
-
Nieuwoudt, A.1
Massoud, Y.2
-
5
-
-
33646434505
-
84% Catalyst activity of water-assisted growth of single walled carbon nanotube forest characterization by a statistical and macroscopic approach
-
D. N. Futaba, K. Hata, T. Namai, T. Yamada, K. Mizuno, Y. Hayamizu, M. Yumura, and S. Iijima, "84% Catalyst activity of water-assisted growth of single walled carbon nanotube forest characterization by a statistical and macroscopic approach," J. Phys. Chem. B, vol. 110, pp. 8035-8038, 2006.
-
(2006)
J. Phys. Chem. B
, vol.110
, pp. 8035-8038
-
-
Futaba, D.N.1
Hata, K.2
Namai, T.3
Yamada, T.4
Mizuno, K.5
Hayamizu, Y.6
Yumura, M.7
Iijima, S.8
-
6
-
-
22944445224
-
Large-scale separation of metallic and semiconducting single-walled carbon nanotubes
-
DOI 10.1021/ja051774o
-
Y.Maeda, S. Kimura,M.Kanda,Y.Hirashima, T.Hasegawa, T.Wakahara, Y. F. Lian, T. Nakahodo, T. Tsuchiya, T. Akasaka, J. Lu, X. W. Zhang, Z. X. Gao, Y. P. Yu, S. Nagase, S. Kazaoui, N. Minami, T. Shimizu, H. Tokumoto, and R. Saito, "Large scale separation of metallic and semiconducting single-walled carbon nanotubes," J. Am. Chem. Soc., vol. 127, pp. 10287-10290, 2005. (Pubitemid 41045495)
-
(2005)
Journal of the American Chemical Society
, vol.127
, Issue.29
, pp. 10287-10290
-
-
Maeda, Y.1
Kimura, S.-I.2
Kanda, M.3
Hirashima, Y.4
Hasegawa, T.5
Wakahara, T.6
Lian, Y.7
Nakahodo, T.8
Tsuchiya, T.9
Akasaka, T.10
Lu, J.11
Zhang, X.12
Gao, Z.13
Yu, Y.14
Nagase, S.15
Kazaoui, S.16
Minam, N.17
Shimizu, T.18
Tokumoto, H.19
Saito, R.20
more..
-
7
-
-
61649106078
-
CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes
-
E. Koungmin Ryu, A. Badmaev, C. Wang, A. Lin, N. Patil, L. Gomez, A. Kumar, S. Mitra, H.-S. PhilipWong, and C. Zhou, "CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes," Nano Lett., vol. 9, no. 1, pp. 189-197, 2009.
-
(2009)
Nano Lett.
, vol.9
, Issue.1
, pp. 189-197
-
-
Koungmin Ryu, E.1
Badmaev, A.2
Wang, C.3
Lin, A.4
Patil, N.5
Gomez, L.6
Kumar, A.7
Mitra, S.8
Philipwong, H.-S.9
Zhou, C.10
-
8
-
-
70349595219
-
Highly aligned scalable platinum-decorated single wall carbon nanotube arrays for nanoscale electrical interconnects
-
Y. L. Kim, B. Li, X. An, M. G. Hahm, L. Chen, M. Washington, P. M. Ajayan, S. K. Nayak, A. Busnaina, S. Kar, and Y. J. Jung, "Highly aligned scalable platinum-decorated single wall carbon nanotube arrays for nanoscale electrical interconnects," ACS Nano, vol. 3, no. 9, pp. 2818-2826, 2009.
-
(2009)
ACS Nano
, vol.3
, Issue.9
, pp. 2818-2826
-
-
Kim, Y.L.1
Li, B.2
An, X.3
Hahm, M.G.4
Chen, L.5
Washington, M.6
Ajayan, P.M.7
Nayak, S.K.8
Busnaina, A.9
Kar, S.10
Jung, Y.J.11
-
9
-
-
0034863491
-
Ultra-low power DLMS adaptive filter for hearing aid applications
-
H. Kim and K. Roy, "Ultra-low power DLMS adaptive filter for hearing aid applications," in Proc. Int. Symp. Low Power Electron. Design, 2001, pp. 352-357.
-
(2001)
Proc. Int. Symp. Low Power Electron. Design
, pp. 352-357
-
-
Kim, H.1
Roy, K.2
-
10
-
-
34548857452
-
A 25μW 100kS/s 12b ADC for wireless micro-sensor applications
-
Feb.
-
N. Verma and A. P. Chandrakasan, "A 25μW 100kS/s 12b ADC for wireless micro-sensor applications," in Proc. IEEE ISSCC, Feb. 2006, pp. 222-223.
-
(2006)
Proc. ISSCC
, pp. 222-223
-
-
Verma, N.1
Chandrakasan, A.P.2
-
11
-
-
25144514874
-
Modeling and sizing for minimum energy operation in subthreshold circuits
-
Sep.
-
B. H. Calhoun, A.Wang, and A. Chandrakasan, "Modeling and sizing for minimum energy operation in subthreshold circuits," IEEE J. Solid-State Circuits, vol. 40, no. 9, pp. 1778-1786, Sep. 2005.
-
(2005)
IEEE J. Solid-State Circuits
, vol.40
, Issue.9
, pp. 1778-1786
-
-
Calhoun, B.H.1
Wang, A.2
Chandrakasan, A.3
-
12
-
-
0026901563
-
CMOS device modeling for subthreshold circuits
-
Aug.
-
M. Godfrey, "CMOS device modeling for subthreshold circuits," IEEE Trans. Circuits Syst., vol. 39, no. 8, pp. 532-539, Aug. 1992.
-
(1992)
IEEE Trans. Circuits Syst.
, vol.39
, Issue.8
, pp. 532-539
-
-
Godfrey, M.1
-
13
-
-
4444275443
-
Double gate-MOSFET subthreshold circuit for ultralow power applications
-
Sep.
-
J. Kim and K. Roy, "Double gate-MOSFET subthreshold circuit for ultralow power applications," IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1468-1474, Sep. 2004.
-
(2004)
IEEE Trans. Electron Devices
, vol.51
, Issue.9
, pp. 1468-1474
-
-
Kim, J.1
Roy, K.2
-
14
-
-
0033873392
-
Modeling of interconnect capacitance, delay, and crosstalk in VLSI
-
Feb.
-
S. C. Wong, G. Y. Lee, and D. Y. Ma, "Modeling of interconnect capacitance, delay, and crosstalk in VLSI," IEEE Trans. Semicond. Manuf., vol. 13, no. 1, pp. 108-111, Feb. 2000.
-
(2000)
IEEE Trans. Semicond. Manuf.
, vol.13
, Issue.1
, pp. 108-111
-
-
Wong, S.C.1
Lee, G.Y.2
Ma, D.Y.3
-
15
-
-
2342459264
-
An RF circuit model for carbon nanotubes
-
Mar.
-
P. J. Burke, "An RF circuit model for carbon nanotubes," IEEE Trans. Nanotechnol., vol. 2, no. 1, pp. 55-58, Mar. 2003.
-
(2003)
IEEE Trans. Nanotechnol.
, vol.2
, Issue.1
, pp. 55-58
-
-
Burke, P.J.1
-
17
-
-
79551653894
-
-
Nanoscale Integration and Modeling (NIMO), Group Arizona State University. [Online]. Available
-
Predictive Technology Models, Nanoscale Integration and Modeling (NIMO) Group, Arizona State University. [Online]. Available: http://ptm.asu.edu/ modelcard/22nm-MGK.pm
-
-
-
|