Compact distributed RLC interconnect models - Part IV: Unified models for time delay, crosstalk, and repeater insertion

IEEE Transactions on Electron Devices

Volumn 50, Issue 4, 2003, Pages 1094-1102

  Venkatesan, Raguraman ^a   Davis, Jeffrey A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Crosstalk; Delay effects; Inductance; Interconnections; Repeaters; RLC circuits; Time domain analysis; Transmission line theory

Indexed keywords

CAPACITANCE; CROSSTALK; ELECTRIC LOADS; INDUCTANCE; TELECOMMUNICATION REPEATERS; TIME DOMAIN ANALYSIS; TRANSMISSION LINE THEORY;

DELAY EFFECTS;

TRANSIENTS;

EID: 0037818361     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.812509     Document Type: Article

References (9)

1. J. A. Davis and J. D. Meindl, "Compact distributed RLC interconnect models - Part I: Single line transient, time delay and overshoot expressions," IEEE Trans. Electron Devices, vol. 47, pp. 2068-2077, Nov. 2000.
2. _, "Compact distributed RLC interconnect models - Part II: Coupled line transient expressions and peak crosstalk in multilevel interconnect networks," IEEE Trans. Electron Devices, vol. 47, pp. 2078-2087, Nov. 2000.
3. R. Venkatesan, J. A. Davis, and J. D. Meindl, "Compact distributed RLC interconnect models -Part III: Transients in single and coupled lines with capacitive load termination," IEEE Trans. Electron Devices, vol. 50, pp. 1081-1093, Apr. 2003.
4. T. Sakurai, "Closed form expressions for interconnection delay, coupling and crosstalk in VLSI's," IEEE Trans. Electron Devices, vol. 40, pp. 118-124,Jan. 1993.
5. Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI Syst., vol. 8. pp. 195-206, Apr. 2000.
6. R. Venkatesan, "Multilevel interconnect architectures for gigascale integration (GSI)," Ph.D. dissertation, Georgia Inst. Technol., Atlanta. Feb. 2003.
7. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI. Reading. MA: Addison-Wesley, 1990, pp. 194-225.
8. Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, "A new analytical delay and noise model for on-chip RLC interconnect." in IEDM Tech. Dig., San Francisco, CA, 2000, pp. 823-826.
9. W. H. Press, S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C. Cambridge, U.K.: Cambridge Univ. Press, 1992.