-
1
-
-
37849186026
-
A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications
-
DOI 10.1109/TCSI.2006.884463
-
H. Y. Yang and R. Sarpeshkar, "A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical application," IEEE Trans. Circuits Syst. I, vol. 53, pp. 2349-2356, Nov. 2006. (Pubitemid 44824314)
-
(2006)
IEEE Transactions on Circuits and Systems I: Regular Papers
, vol.53
, Issue.11
, pp. 2349-2356
-
-
Yang, H.Y.1
Sarpeshkar, R.2
-
2
-
-
84869165862
-
Power efficient ADCs for biomedical signal acquisition
-
A. N. Laskovski, Ed. New York: In-tech
-
R. P. Alberto, D. R. Manuel, and M. Fernando, "Power efficient ADCs for biomedical signal acquisition," in Biomedical Eng., Trends in Electronics, Commun. and Software, A. N. Laskovski, Ed. New York: In-tech, 2011, pp. 171-192.
-
(2011)
Biomedical Eng., Trends in Electronics, Commun. and Software
, pp. 171-192
-
-
Alberto, R.P.1
Manuel, D.R.2
Fernando, M.3
-
3
-
-
78650335108
-
A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission
-
A. Bonfanti, M. Ceravolo, G. Zambra, R. Gusmeroli, T. Borghi, A. S. Spinelli, and A. L. Lacaita, "A multi-channel low-power IC for neural spike recording with data compression and narrowband 400-MHz MC-FSK wireless transmission," in Proc. ESSCIRC, 2010, pp. 330-333.
-
(2010)
Proc. ESSCIRC
, pp. 330-333
-
-
Bonfanti, A.1
Ceravolo, M.2
Zambra, G.3
Gusmeroli, R.4
Borghi, T.5
Spinelli, A.S.6
Lacaita, A.L.7
-
4
-
-
79955792575
-
Adaptive resolution ADC array for an implantable neural sensor
-
Apr.
-
S. O'Driscoll, K. V. Shenoy, and T. H. Meng, "Adaptive resolution ADC array for an implantable neural sensor," IEEE Trans. Biomed. Circuits Syst., vol. 5, pp. 120-130, Apr. 2011.
-
(2011)
IEEE Trans. Biomed. Circuits Syst.
, vol.5
, pp. 120-130
-
-
O'Driscoll, S.1
Shenoy, K.V.2
Meng, T.H.3
-
5
-
-
57849122662
-
An over-60-dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain
-
Dec
-
B. R. Gregoire and U. Moon, "An over-60-dB true rail-to-rail performance using correlated level shifting and an opamp with only 30 dB loop gain," IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2620-2630, Dec. 2008.
-
(2008)
IEEE J. Solid-State Circuits
, vol.43
, Issue.12
, pp. 2620-2630
-
-
Gregoire, B.R.1
Moon, U.2
-
6
-
-
78649634547
-
A 10-b 50-MS/s 820- W SAR ADC with on-chip digital calibration
-
Dec.
-
M. Yoshika, K. Ishikawa, T. Takayama, and S. Tsukamoto, "A 10-b 50-MS/s 820- W SAR ADC with on-chip digital calibration," IEEE Trans. Biomed. Circuits Syst., vol. 4, pp. 410-416, Dec. 2010.
-
(2010)
IEEE Trans. Biomed. Circuits Syst.
, vol.4
, pp. 410-416
-
-
Yoshika, M.1
Ishikawa, K.2
Takayama, T.3
Tsukamoto, S.4
-
7
-
-
33845616534
-
A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13- m CMOS
-
S. W. M. Chen and R. W. Brodersen, "A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13- m CMOS," in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 574-575.
-
(2006)
IEEE ISSCC Dig. Tech. Papers
, pp. 574-575
-
-
Chen, S.W.M.1
Brodersen, R.W.2
-
8
-
-
77952180756
-
A 10 b 50 MS/s 820 W SAR ADC with on-chip digital calibration
-
M. Yoshioka, K. Ishikawa, T. Takayama, and S. Tsukamoto, "A 10 b 50 MS/s 820 W SAR ADC with on-chip digital calibration," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 384-385.
-
(2010)
IEEE ISSCC Dig. Tech. Papers
, pp. 384-385
-
-
Yoshioka, M.1
Ishikawa, K.2
Takayama, T.3
Tsukamoto, S.4
-
9
-
-
76249095244
-
A 10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-medical applications
-
W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, "A 10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-medical applications," in Proc. IEEE A-SSCC, 2009, pp. 149-152.
-
(2009)
Proc. IEEE A-SSCC
, pp. 149-152
-
-
Pang, W.Y.1
Wang, C.S.2
Chang, Y.K.3
Chou, N.K.4
Wang, C.K.5
-
10
-
-
77950287759
-
A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure
-
Apr.
-
C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, "A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure," IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, pp. 731-740
-
-
Liu, C.C.1
Chang, S.J.2
Huang, G.Y.3
Lin, Y.Z.4
-
11
-
-
77953275222
-
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
-
Jun.
-
Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, "A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS," IEEE J. Solid-State Circuits, vol. 45, pp. 1111-1121, Jun. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, pp. 1111-1121
-
-
Zhu, Y.1
Chan, C.-H.2
Chio, U.-F.3
Sin, S.-W.4
U, S.-P.5
Martins, R.P.6
Maloberti, F.7
-
12
-
-
82955194670
-
A high energy-efficiency SAR ADC based on partial floating capacitor switching technique
-
C. H. Kuo and C. E. Hsieh, "A high energy-efficiency SAR ADC based on partial floating capacitor switching technique," in Proc. IEEE ESS-CIRC, 2011, pp. 475-478.
-
(2011)
Proc. IEEE ESS-CIRC
, pp. 475-478
-
-
Kuo, C.H.1
Hsieh, C.E.2
-
13
-
-
34748918257
-
A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC
-
Oct
-
H. C. Hong and G. M. Lee, "A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC," IEEE J. Solid-State Circuits, vol. 42, pp. 2161-2167, Oct. 2007.
-
(2007)
IEEE J. Solid-State Circuits
, vol.42
, pp. 2161-2167
-
-
Hong, H.C.1
Lee, G.M.2
-
14
-
-
82955241247
-
A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13- m CMOS for medical implant devices
-
D. Zhang, A. Bhide, and A. Alvandpour, "A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13- m CMOS for medical implant devices," in Proc. IEEE ESSCIRC, 2011, pp. 467-470.
-
(2011)
Proc. IEEE ESSCIRC
, pp. 467-470
-
-
Zhang, D.1
Bhide, A.2
Alvandpour, A.3
-
15
-
-
82955164411
-
A 0.5 v 20 fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application
-
S. I. Chang, K. Al-Ashmouny, and E. Yoon, "A 0.5 V 20 fJ/conversion-step rail-to-rail SAR ADC with programmable time-delayed control units for low-power biomedical application," in Proc. IEEE ESSCIRC, 2011, pp. 339-342.
-
(2011)
Proc. IEEE ESSCIRC
, pp. 339-342
-
-
Chang, S.I.1
Al-Ashmouny, K.2
Yoon, E.3
-
16
-
-
80455150164
-
A 0.5 v 1 kS/s 2.5 nW 8.52-ENOB 6.8 fJ/conversion-step SAR ADC for biomedical application
-
T. C. Lu, L. D. Van, C. S. Lin, and C. M. Huang, "A 0.5 V 1 kS/s 2.5 nW 8.52-ENOB 6.8 fJ/conversion-step SAR ADC for biomedical application," in Proc. IEEE CICC, 2011, pp. 1-4.
-
(2011)
Proc. IEEE CICC
, pp. 1-4
-
-
Lu, T.C.1
Van, L.D.2
Lin, C.S.3
Huang, C.M.4
-
17
-
-
77952141253
-
A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation
-
C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, C. M. Huang, C. H. Huang, L. Bu, and C. C. Tsai, "A 10 b 100 MS/s 1.13 mW SAR ADC with binary-scaled error compensation," in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 386-387.
-
(2010)
IEEE ISSCC Dig. Tech. Papers
, pp. 386-387
-
-
Liu, C.C.1
Chang, S.J.2
Huang, G.Y.3
Lin, Y.Z.4
Huang, C.M.5
Huang, C.H.6
Bu, L.7
Tsai, C.C.8
-
18
-
-
79960847584
-
A 550-mW 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction
-
Aug
-
S. H. Cho, C. K. Lee, J. K. Kwon, and S. T. Ryu, "A 550-mW 10-b 40-MS/s SAR ADC with multistep addition-only digital error correction," IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1-12, Aug. 2011.
-
(2011)
IEEE J. Solid-State Circuits
, vol.46
, Issue.8
, pp. 1-12
-
-
Cho, S.H.1
Lee, C.K.2
Kwon, J.K.3
Ryu, S.T.4
-
19
-
-
77957982668
-
A 1 v 11 fJ/conversion-step 10 bit 10 MS/s asynchronous SAR-ADC in 0.18 m CMOS
-
C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, and C. M. Huang, "A 1 V 11 fJ/conversion-step 10 bit 10 MS/s asynchronous SAR-ADC in 0.18 m CMOS," in IEEE Symp. VLSI Circuits Dig., 2010, pp. 241-242.
-
(2010)
IEEE Symp. VLSI Circuits Dig.
, pp. 241-242
-
-
Liu, C.C.1
Chang, S.J.2
Huang, G.Y.3
Lin, Y.Z.4
Huang, C.M.5
-
20
-
-
79955718294
-
A resolution-reconfigurable 5-to-10 b 0.4-to-1 v power scalable SAR ADC
-
M. Yip and A. P. Chandrakasan, "A resolution-reconfigurable 5-to-10 b 0.4-to-1 V power scalable SAR ADC," in IEEE ISSCC Dig. Tech. Papers, 2011, pp. 190-192.
-
(2011)
IEEE ISSCC Dig. Tech. Papers
, pp. 190-192
-
-
Yip, M.1
Chandrakasan, A.P.2
-
21
-
-
79952071655
-
A 21 fJ/con-version-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface
-
Mar
-
S. K. Lee, S. J. Park, Y. Suh, H. J. Park, and J. Y. Sim, "A 21 fJ/con-version-step 100 kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface," IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 651-659, Mar. 2011.
-
(2011)
IEEE J. Solid-State Circuits
, vol.46
, Issue.3
, pp. 651-659
-
-
Lee, S.K.1
Park, S.J.2
Suh, Y.3
Park, H.J.4
Sim, J.Y.5
-
22
-
-
77951681747
-
A 10-bit charge-redistribution ADC consuming 1.9 W at 1 MS/s
-
May
-
M. V. Elzakker, E. V. Tuijl, P. Geradets, D. Schinkel, E. A. M. Klumperink, and B. Nauta, "A 10-bit charge-redistribution ADC consuming 1.9 W at 1 MS/s," IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.5
, pp. 1007-1015
-
-
Elzakker, M.V.1
Tuijl, E.V.2
Geradets, P.3
Schinkel, D.4
Klumperink, E.A.M.5
Nauta, B.6
-
23
-
-
0032664038
-
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
-
May
-
A. M. Abo and P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, Issue.5
, pp. 599-606
-
-
Abo, A.M.1
Gray, P.R.2
-
24
-
-
33947675327
-
500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC
-
DOI 10.1109/JSSC.2007.892169
-
B. P. Ginsburg and A. P. Chandrakasan, "550-MS/s 5-b ADC in 65-nm CMOS with split capacitor array DAC," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007. (Pubitemid 46495390)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.4
, pp. 739-747
-
-
Ginsburg, B.P.1
Chandrakasan, A.P.2
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