A 10-b 50-MS/s 820-μW SAR ADC with on-chip digital calibration

IEEE Transactions on Biomedical Circuits and Systems

Volumn 4, Issue 6 PART 1, 2010, Pages 410-416

  Yoshioka, Masato ^a   Ishikawa, Kiyoshi ^a   Takayama, Takeshi ^a   Tsukamoto, Sanroku ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

Analog to digital converter (ADC); digital calibration; successive approximation register

Indexed keywords

ACTIVE AREA; ANALOG TO DIGITAL CONVERTERS; COMPLEMENTARY METAL OXIDE SEMICONDUCTORS; DIGITAL CALIBRATIONS; DIGITAL-TO-ANALOG CONVERTERS; EXPONENTIAL INCREASE; FIGURE OF MERIT; INPUT FREQUENCY; INTERNAL CLOCK; LOAD CAPACITANCE; MIM CAPACITORS; NOISE RESTRICTION; NYQUIST; OFFSET CANCELLATION; ON CHIPS; PVT VARIATIONS; SAR ADC; SUCCESSIVE APPROXIMATION REGISTER;

ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; CALIBRATION; CAPACITORS; FREQUENCY CONVERTERS; HYBRID COMPUTERS; METALLIC COMPOUNDS; MIM DEVICES; MOS DEVICES;

DIGITAL CIRCUITS;

EID: 78649634547     PISSN: 19324545     EISSN: None     Source Type: Journal    
DOI: 10.1109/TBCAS.2010.2081362     Document Type: Conference Paper

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