A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC

IEEE Journal of Solid-State Circuits

Volumn 42, Issue 10, 2007, Pages 2161-2168

  Hong, Hao Chiao ^a,b   Lee, Guo Ming ^b  

^a IEEE

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

W design; ADC; Energy efficient; Low power; Low supply voltage; Successive approximation

Indexed keywords

APPROXIMATION THEORY; BANDWIDTH; ELECTRIC DISTORTION; ENERGY EFFICIENCY; NYQUIST DIAGRAMS; SIGNAL TO NOISE RATIO;

CONVERSION-STEP; LOW SUPPLY VOLTAGE; NYQUIST BANDWIDTH; SUCCESSIVE APPROXIMATION ADC;

ANALOG TO DIGITAL CONVERSION;

EID: 34748918257     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2007.905237     Document Type: Conference Paper

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