A 1V 11fJ/Conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18μm CMOS

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2010, Pages 241-242

  Liu, Chun Cheng ^a   Chang, Soon Jyh ^a   Huang, Guan Ying ^a   Lin, Ying Zu ^a   Huang, Chung Ming ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b HIMAX TECHNOLOGIES INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGY; SAR ADC; VARIABLE WINDOWS;

CMOS INTEGRATED CIRCUITS;

VLSI CIRCUITS;

EID: 77957982668     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2010.5560283     Document Type: Conference Paper

References (4)

1. C. C. Liu, S. J. Chang, G. Y. Huang and Y. Z. Lin, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process," IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 236-237.
2. J. J. Kang and M. P. Flynn, "A 12b 11MS/s successive approximation ADC with two comparators in 0.13μm CMOS," IEEE Symposium on VLSI Circuits, Jun. 2009, pp. 240-241.
3. W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou and C. K. Wang, "A 10-bit 500-KS/s Low Power SAR ADC with Splitting Comparator for Bio-Medical Applications," IEEE Asian Solid-State Circuits Conference, pp. 149-152, Nov. 2009.
4. B. P. Ginsburg and A. P. Chandrakasan, "500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC," IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.