A resolution-reconfigurable 5-to-10b 0.4-to-1V power scalable SAR ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2011, Pages 190-191

  Yip, Marcus ^a   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; SENSOR NETWORKS;

CONSUMING POWER; DYNAMIC RANGE; ENERGY CONSTRAINED SYSTEMS; POWER SCALABLE; RECONFIGURABLE; REDUCING SYSTEMS; SAMPLE RATE; SAR ADC;

ENERGY EFFICIENCY;

EID: 79955718294     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2011.5746277     Document Type: Conference Paper

References (6)

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2. G. Van der Plas and B. Verbruggen, "A 150MS/s 133μW 7b ADC in 90nm Digital CMOS Using a Comparator-Based Asynchronous Binary-Search Sub-ADC," ISSCC Dig. Tech. Papers, pp. 242-243, Feb., 2008.
3. S. O'Driscoll and T.H. Meng, "Adaptive Resolution ADC Array for Neural Implant," Proc. IEEE EMBC, pp. 1053-1056, Sep., 2009.
4. D.C. Daly and A.P. Chandrakasan, "A 6b 0.2-to-0.9V Highly Digital Flash ADC with Comparator Redundancy," ISSCC Dig. Tech. Papers, pp. 554-555, Feb., 2008.
5. N. Verma and A.P. Chandrakasan, "A 25μW 100kS/s 12b ADC for Wireless Micro-Sensor Applications," ISSCC Dig. Tech. Papers, pp. 822-823, Feb., 2006.
6. B.P. Ginsburg and A.P. Chandrakasan, "An Energy-Efficient Charge Recycling Approach for a SAR Converter with Capacitive DAC," Proc. IEEE Int. Symp. Circuits and Systems, pp. 184-187, May, 2005.