A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 386-387

  Liu, Chun Cheng ^a   Chang, Soon Jyh ^a   Huang, Guan Ying ^a   Lin, Ying Zu ^a   Huang, Chung Ming ^b   Huang, Chih Hao ^b   Bu, Linkai ^b   Tsai, Chih Chung ^b  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b HIMAX TECHNOLOGIES INC   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ADVANCED PROCESS; CAPACITOR NETWORK; CMOS TECHNOLOGY; DESIGN COMPLEXITY; HARDWARE OVERHEADS; INTERCONNECT LINES; LOGIC DELAYS; NON-BINARY; POWER EFFICIENCY; REFERENCE VOLTAGES; ROUTING PATH; SAMPLING RATES; SAR ADC; SETTLING ERROR; SETTLING TIME; SHORT TIME INTERVALS; SMALL AREA;

CHARGE TRANSFER; ION EXCHANGE;

ERROR COMPENSATION;

EID: 77952141253     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433970     Document Type: Conference Paper

References (5)

1. F. Kuttner, "A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS," ISSCC Dig. Tech. Papers, pp. 176-177, Feb., 2002,.
2. J. Craninckx and G. Van der Plas, "A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-sharing SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 246-247, Feb., 2007.
3. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, J. Craninckx, "An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS," ISSCC Dig. Tech. Papers, pp. 238-239, Feb. 2008.
4. C. C. Liu, S. J. Chang, G. Y. Huang, Y. Z. Lin, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process," Symp. on VLSI Circuits, pp. 236-237, Jun. 2009,.
5. M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, "A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS," IEEE ISSCC Dig. Tech. Papers, pp. 250-251, Feb., 2008.