A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure

IEEE Journal of Solid-State Circuits

Volumn 45, Issue 4, 2010, Pages 731-740

  Liu, Chun Cheng ^a   Chang, Soon Jyh ^a   Huang, Guan Ying ^a   Lin, Ying Zu ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Analog to digital converter; Energy efficient; Low power; Successive approximation register

Indexed keywords

ACTIVE AREA; ANALOG TO DIGITAL CONVERTERS; CAPACITOR SWITCHING; CMOS TECHNOLOGY; COMMON MODE VOLTAGE; ENERGY EFFICIENT; FIGURE OF MERIT; LOW POWER; SAR ADC; SUCCESSIVE APPROXIMATION REGISTER; SWITCHING ENERGY;

ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; SWITCHING;

MULTICARRIER MODULATION;

EID: 77950287759     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2010.2042254     Document Type: Conference Paper

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