A 10b 50MS/s 820μW SAR ADC with on-chip digital calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 53, Issue , 2010, Pages 384-385

  Yoshioka, Masato ^a   Ishikawa, Kiyoshi ^a   Takayama, Takeshi ^a   Tsukamoto, Sanroku ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK FREQUENCY; CLOCK GENERATION; CMOS TECHNOLOGY; DELAY VARIATION; DIGITAL CALIBRATIONS; DIGITAL-TO-ANALOG CONVERTERS; HIGH-RESOLUTION SAR; INTERNAL CLOCK; LINEARITY ERRORS; OFFSET CALIBRATION; ON CHIPS; POWER EFFICIENT; PVT VARIATIONS; RAPID GROWTH; SAMPLING RATES; SAR ADC; SCALED CMOS; STATIC CURRENTS;

ANALOG TO DIGITAL CONVERSION; CALIBRATION; CAPACITANCE; CAPACITORS; CMOS INTEGRATED CIRCUITS; ELECTRIC CONVERTERS; ENERGY EFFICIENCY; HYBRID COMPUTERS; MEDICAL APPLICATIONS; OPERATIONAL AMPLIFIERS;

CLOCKS;

EID: 77952180756     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2010.5433965     Document Type: Conference Paper

References (4)

1. V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, J. Craninckx, An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS, IEEE International Solid-State Circuits Conference, vol. 51, pp. 238-239, February 2008.
2. A. Agnes, E. Bonizzoni, P. Malcovati, F. Maloberti, A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time-Domain Comparator, IEEE International Solid-State Circuits Conference, vol. 51, pp. 246-247, February 2008.
3. Y. Chen et al, Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC, 2009 IEEE Custom Integrated Circuits Conference, pp. 279-282, September 2009
4. Hau-Seung Lee, David A. Hodges, Paul R. Gray; A self-calibrating 15 bit CMOS A/D converter, IEEE Journal of Solid-State Circuits, vol. 19, pp. 813-819, December 1984. (Pubitemid 15478751)