Thickness and temperature dependence of the leakage current in hafnium-based Si SOI MOSFETs

Microelectronics Reliability

Volumn 52, Issue 12, 2012, Pages 2907-2913

  Kim, Jiseok ^a   Krishnan, Siddarth A ^b   Narayanan, Sudarshan ^a   Chudzik, Michael P ^b   Fischetti, Massimo V ^a  

^a The University of Texas at Dallas   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BARRIER LOWERING; FERMI-DIRAC; FN PLOTS; FOWLER-NORDHEIM TUNNELING; GATE-LEAKAGE CURRENT; HIGH TEMPERATURE; LEAKAGE MECHANISM; METAL-GATE; MOSFETS; N-CHANNEL; OXIDE THICKNESS; POOLE-FRENKEL; SOI-MOSFETS; STRONG NONLINEARITY; TEMPERATURE DEPENDENCE; TEMPERATURE DEPENDENT; THERMAL HEATING;

HAFNIUM;

MOSFET DEVICES;

EID: 84868682747     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2012.06.151     Document Type: Article

References (30)

1. J. Stathis Reliability limits for the gate insulator in CMOS technology IBM J Res Dev 46 2-3 2002 265 286
2. 2 high-κ dielectrics. In: Electron Dev Meet., 2000. IEDM Technical Digest. International; 2000. p. 35-8.
3. G. Wilk, R. Wallace, and J. Anthony High-κ gate dielectrics: current status and materials properties considerations J Appl Phys 89 2001 5243
4. W. Zhu, T. Ma, T. Tamagawa, J. Kim, and Y. Di Current transport in metal/hafnium oxide/silicon structure IEEE Electron Dev Lett 23 2 2002 97 99
5. 2 on silicon Appl Phys Lett 86 2005 202902
6. K. Ng, N. Zhan, C. Kok, M. Poon, and H. Wong Electrical characterization of the hafnium oxide prepared by direct sputtering of Hf in oxygen with rapid thermal annealing Microelec Reliab 43 8 2003 1289 1293
7. 2 gate dielectric stacks Appl Phys Lett 80 2002 1975
8. 2 Appl Phys Lett 85 2004 3289
9. Chudzik M, Doris B, Mo R, Sleight J, Cartier E, Dewan C et al. High-performance high-κ/metal gates for 45 nm cmos and beyond with gate-first processing. In: VLSI Technology, 2007 IEEE Symposium on, IEEE; 2007. p. 194-5.
10. Houssa M, Naili M, Afanasiev V, Heyns M, Stesmans A. Electrical and physical characterization of high-κ dielectric layers. In: VLSI Technology, Systems, and Applications, 2001. Proceedings of Technical Papers. 2001 International Symposium on, IEEE; 2001. p. 196-9.
11. Taur Y, Ning T. Fundamentals of Modern VLSI Design; 1998.
12. J. Robertson Band offsets of wide-band-gap oxides and implications for future electronic devices J Vac Sci Technol B 18 2000 1785
13. B. Sen, H. Wong, V. Filip, H. Choi, C. Sarkar, and M. Chan Current transport and high-field reliability of aluminum/hafnium oxide/silicon structure Thin Solid Films 504 1-2 2006 312 316
14. W. Wang, N. Gu, J. Sun, and P. Mazumder Gate current modeling of high-κ stack nanoscale MOSFETs Solid State Electron 50 9-10 2006 1489 1494
15. F. Stern Self-consistent results for n-type si inversion layers Phys Rev B 5 12 1972 4891 4899
16. M. Vexler, S. Tyaginov, and A. Shulekin Determination of the hole effective mass in thin silicon dioxide film by means of an analysis of characteristics of a MOS tunnel emitter transistor J Phys: Condens Matter 17 2005 8057
17. + poly-gate pMOSFETs with ultrathin gate oxides IEEE Trans IEEE Trans Electron Dev 47 11 2000 2161
18. 2/Si interface Mater Sci Rep 1 2 1986 65 160
19. A. Zhakharova, V. Ryzhii, and V. Pesotzkii Semiclassical interband tunnelling probability in semiconductor heterostructures Semicond Sci Tech 9 1994 41 48
20. E. Kane Theory of tunneling J Appl Phys 32 1961 83
21. L. Keldysh Behavior of non-metallic crystals in strong electric fields Soviet Phys JETP 6 1958 763
22. F. Rana, S. Tiwari, and D. Buchanan Self-consistent modeling of accumulation layers and tunneling currents through very thin oxides Appl Phys Lett 69 1996 1104
23. S. Narayanan, C. Sachs, and M. Fischetti Study of performance and leakage currents in nanometer-scale bulk, SOI and double-gate MOSFETs J Comp Elec 7 1 2008 24 27
24. Y. Zhang, M. Fischetti, B. Sorée, W. Magnus, M. Heyns, and M. Meuris Physical modeling of strain-dependent hole mobility in Ge p-channel inversion layers J Appl Phys 106 2009 083704
25. 2 thin films J Appl Phys 98 2005 113701
26. 2 stack Int Reliab Phys Symp 2004 181 187
27. 2/TiN gate stacks during positive-bias temperature stress Int Reliab Phys Symp 2009 486 492
28. A. Kerber, and E. Cartier Reliability challenges for CMOS technology qualifications with hafnium oxide/titanium nitride gate stacks IEEE Trans Dev Mater Reliab 9 2 2009
29. B.P. Linder, E. Cartier, S. Krishnan, and J.H. Stathis The effect of interface thickness of high-k/metal gate stacks on NFET dielectric reliability Int Reliab Phys Symp 2009 510 513
30. A. Kerber, E. Cartier, B.P. Linder, S.A. Krishnan, and T. Nigam TDDB failure distribution of metal gate/high-k CMOS devices on SOI substrates Int Reliab Phys Symp 2009 505 509