Performance evaluation of III-V nanowire transistors

IEEE Transactions on Electron Devices

Volumn 59, Issue 9, 2012, Pages 2375-2382

  Jansson, Kristofer ^a   Lind, Erik ^a   Wernersson, Lars Erik ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

Field effect transistor (FET); InAs; modeling; nanowires (NWs); roadmap

Indexed keywords

DEVICE FABRICATIONS; EMERGING TECHNOLOGIES; GATE LENGTH; INAS; INTRINSIC PROPERTY; INTRINSIC TRANSISTOR; LOW-POWER DISSIPATION; NANOWIRE TRANSISTORS; PARASITIC CAPACITANCE; PARASITIC ELEMENT; PERFORMANCE EVALUATION; RF PERFORMANCE; ROADMAP; SCALING RULES; STRUCTURAL PARAMETER; TECHNOLOGY NODES; TERA HERTZ; TRANSISTOR ARCHITECTURE; TRANSISTOR STRUCTURE;

CAPACITANCE; FIELD EFFECT TRANSISTORS; INDIUM ARSENIDE; MODELS; NANOWIRES; OPTIMIZATION;

TRANSISTORS;

EID: 84865521712     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2204757     Document Type: Article

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