Improvement potential and equalization example for multidrop DRAM memory buses

IEEE Transactions on Advanced Packaging

Volumn 32, Issue 3, 2009, Pages 675-682

  Fredriksson, Henrik ^a   Svensson, Christer ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Adaptive equalizers; Channel capacity; DRAM; Multidrop bus

Indexed keywords

ADAPTIVE EQUALIZERS; BITRATES; BUS STRUCTURES; CHANNEL STRUCTURES; CMOS TEST; DATA CAPACITY; DRAM; DRAM MEMORIES; FUNDAMENTAL LIMITS; LOW LATENCY; MEMORY CIRCUITS; MULTIDROP BUS; SIGNAL FREQUENCIES;

CHANNEL CAPACITY; EQUALIZERS; SIGNAL PROCESSING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 68949189534     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/TADVP.2009.2013818     Document Type: Article

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