The Virtual Write Queue: Coordinating DRAM and last-level cache policies

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2010, Pages 72-82

  Stuecheli, Jeffrey ^a,b   Kaseridis, Dimitris ^a   Daly, David ^c   Hunter, Hillery C ^c   John, Lizy K ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b IBM   (United States)

^c IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LIMITING EFFECTS; MAIN MEMORY; MANY-CORE ARCHITECTURE; MEMORY CONTROLLER; MEMORY LATENCIES; MEMORY OPTIMIZATION; NEW APPROACHES; SYSTEM CYCLE; SYSTEM LEVELS; THROUGHPUT IMPROVEMENT;

COMPUTER ARCHITECTURE; COMPUTERS; DYNAMIC RANDOM ACCESS STORAGE; QUEUEING THEORY;

CACHE MEMORY;

EID: 77954992165     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1815961.1815972     Document Type: Conference Paper

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