Hierarchical multi-bank DRAM: A high-performance architecture for memory integrated with processors

Proceedings of the Conference on Advanced Research in VLSI

Volumn , Issue , 1997, Pages 303-319

  Yamauchi, Tadaaki ^a   Hammond, Lance ^a   Olukotun, Kunle ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DECODING; HIERARCHICAL SYSTEMS; PARALLEL PROCESSING SYSTEMS;

DYNAMIC RANDOM ACCESS MEMORY (DRAM);

RANDOM ACCESS STORAGE;

EID: 0031363421     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)