Understanding the energy consumption of Dynamic Random Access Memories

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 363-374

  Vogelsang, Thomas ^a  

^a RAMBUS INC   (United States)

Author keywords

DRAM; Power

Indexed keywords

BANDWIDTH REQUIREMENT; DATA SHEETS; DATA-SHEET VALUES; DRAM; DRAM TECHNOLOGY; DYNAMIC RANDOM ACCESS MEMORY; ENERGY CONSUMPTION; LARGE SYSTEM; POWER; POWER MODEL; POWER REDUCTIONS; POWER USAGE; ROADMAP; TECHNOLOGY AND OPERATIONS; TOTAL ENERGY CONSUMPTION;

ENERGY UTILIZATION; EXTRAPOLATION;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 79951702954     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.42     Document Type: Conference Paper

References (23)

1. L. Minas and B. Ellison, The Problem of Power Consumption in Servers. Hillsboro; Intel Press, 2009.
2. S. Thoziyoor, J. Ahn, M. Monchiero, J. Brockman and N. Jouppi., "A comprehensive memory modeling tool and its application to the design and analysis of future memory hierarchies", Proceedings ISCA 2008
3. S. Thoziyoor, N. Muralimanohar, J. Ahn and N. Jouppi., "CACTI 5.1", HPL-2008-20, HP Laboratories Palo Alto 2008, [Online] Hewlett-Packard Inc., 2008 [Cited 5/24/2010] http://etd.nd.edu/ETDdb/theses/available/etd- 07122008-005947/unrestricted/ThoziyoorS072008.pdf
4. S. Thoziyoor, "A Comprehensive Memory Modeling Tool For Design And Analysis Of Future Memory Hierarchies", Ph.D. Dissertation University of Notre Dame 2008, [Online] University of Notre Dame, 2008 [Cited 5/24/2010] http://etd.nd.edu/ETDdb/theses/available/etd-07122008-005947/unrestricted/ ThoziyoorS072008.pdf
5. M. Nakamura, T. Takahashi, T. Akiba, G. Kitsukawa, M. Morino, T. Sekiguchi, I. Asano, K. Komatsuzaki, Y. Tadaki, C. Songsu, K. Kajigaya, T. Tachibana and K. Satoh, "A 29ns 64Mb DRAM with Hierarchical Array Architecture", International Solid-State Circuits Conference, pp. 246-247, 1995
6. Y. Nitta, N. Sakashita, K. Shimomura, F. Okuda, H. Shimano, S. Yamakawa, A. Furukawa, K. Kise, H. Watanabe, Y. Toyoda, T. Fukada, M. Hasegawa, M. Tsukude, K. Arimoto, S. Baba, Y. Tomita, S. Komori, K. Kyuma and H. Abe, "A 1.6GB/s Data-Rate 1Gb Synchronous DRAM with Hierarchical Square-Shaped Memory Block and Distributed Bank Architecture", International Solid-State Circuits Conference, pp. 376-377, 1996
7. T. Oh, Y. Sohn, S. Bae, M. Park, J. Lim, Y. Cho, D. Kim, D. Kim, H. Kim, H. Kim, J. Kim, J. Kim, Y. Kim, B. Kim, S. Kwak, J. Lee, J. Lee, C. Shin, Y. Yang, B. Cho, S. Bang, H. Yang, Y. Choi, G. Moon, C. Park, S. Hwang, J. Lim, K. Park, J. Choi and Y. Jun, "A 7Gb/s/pin GDDR5 SDRAM with 2.5ns Bank-to-Bank Active Time and No Bank-Group Restriction", International Solid State Circuits Conference, pp. 434-435, 2010
8. B. Jeong, J. Lee, Y. Lee, T. Kang, J. Lee, D. Hong, J. Kim, E. Lee, M. Kim, K. Lee, S. Park, J. Son, S. Lee, S. Yoo, S. Kim, T. Kwon, J. Ahn and Y. Kim, "A 1.35V 4.3GB/s 1Gb LPDDR2 DRAM with controllable repeater and on-the-fly power-cut scheme for low-power and high-speed mobile application", International Solid State Circuits Conference, pp. 132-133, 2009
9. U. Kang, H. Chung, S. Heo, D. Park, H. Lee, J. Kim, S. Ahn, S. Cha, J. Ahn, D. Kwon, J. Lee, H. Joo, W. Kim, D. Jang, N. Kim, J. Choi, T. Chung, J. Yoo, J., C. Kim and Y. Jun, "8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology", Journal of Solid-State Circuits, pp. 111-119, Jan. 2010
10. Y. Moon, Y. Cho, H. Lee, B. Jeong, S. Hyun, B. Kim, I. Jeong, S. Seo, J. Shin, S. Choi, H. Song, J. Choi, K. Kyung, Y. Jun and K. Kim, "1.2V 1.6Gb/s 56nm 6F2 4Gb DDR3 SDRAM with hybrid-I/O sense amplifier and segmented sub-array architecture", International Solid-State Circuits Conference, pp. 128-129, 2009
11. I. Hur and C. Lin, "A comprehensive approach to DRAM power management," International Symposium on High Performance Computer Architecture, pp. 305-316, 2008
12. P. Emma, W. Reohr and M. Meterelliyoz, "Rethinking Refresh: Increasing Availability and Reducing Power in DRAM for Cache Applications," IEEE Micro, pp.47-56, Nov.-Dec. 2008
13. F. Ware and C. Hampel, "Improving Power and Data Efficiency with Threaded Memory Modules", Proceedings of ICCD, 2006
14. H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David and Z. Zhu, "Mini-Rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency", Proceedings of Micro, 2008
15. A. Udipi, N. Muralimanohar, N. Chatterjee, R. Balasubramonian, A. Davis and N. Jouppi, "Rethinking DRAM Design and Organization for Energy-Constrained Multi-Cores", Proceedings ISCA 2010, pp. 175-186, June 2010
16. T. Sunaga, "A Full Bit Prefetch DRAM Sensing Circuit", IEEE Journal of Solid State Circuits, pp. 767-772, June 1996 (Pubitemid 126543790)
17. T. Sunaga, K. Hosokawa, S. H. Dhong and K. Kitamura, "A 64Kb x 32 DRAM for graphics applications", IBM Journal of Research and Development, pp. 43-50, January 1995
18. S. Beamer, C. Sun, Y. Kwon, A. Joshi, C. Batten, V. Stojanovic and, K. Asanovic, "Re-Architecting DRAM Memory Systems with Monolithically Integrated Silicon Photonics", Proceedings ISCA 2010, pp. 129-140, June 2010
19. D. Wang, B. Ganesh, N. Tuaycharoen, K. Baynes, A. Jaleel and B. Jacob, "DRAMsim: A Memory System Simulator." SIGARCH Computer Architecture News, 2005
20. Micron Technologies Inc. System Power Calculator. [Online] Micron Technologies, Inc., 2009. [Cited: 11/11, 2009.] http://www.micron.com/support/ part-info/powercalc.aspx
21. ITRS. 2009 International Technology Roadmap for Semiconductors. [Online] ITRS. [Cited: 01/28, 2010.] http://www.itrs.net/Links/2009ITRS/Home2009.htm
22. Data Sheets 1G DDR2 for parts Samsung K4T1G04(08/16)4QQ, Hynix H5PS1G63EFR and HY5PS1G1631CFP, Micron MT47H64M16, Elpida EDE1116ACBG and Qimonda HYI18T1G160C2 [Online at respective company websites]
23. Data Sheets 1G DDR3 for parts Samsung K4BG04(08/16)46D, Hynix H5TQ1G63AFP, Micron MT41J64M16, Elpida EDJ1116BBSE and Qimonda IDSH1G-04A1F1C [Online at respective company websites]