Fast cycle RAM (FCRAM); A 20-ns random row access, pipe-lined operating DRAM

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 22-25

  Sato, Yasuharu ^a   Suzuki, Takaaki ^a   Aikawa, Tadao ^a   Fujioka, Shin ya ^a   Fujieda, Waichiro ^a   Kobayashi, Hiroyuki ^a   Ikeda, Hitoshi ^a   Nagasawa, Takayuki ^a   Funyu, Akihiro ^a   Fujii, Yasuhiro ^a   Kawasaki, Ken ichi ^a   Yamazaki, Masafumi ^a   Taguchi, Masao ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; MULTIPLEXING; PIPELINE PROCESSING SYSTEMS; TIMING CIRCUITS;

FAST CYCLE RANDOM ACCESS MEMORY (FCRAM);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0031641453     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)