Cached DRAM for ILP processor memory access latency reduction

IEEE Micro

Volumn 21, Issue 4, 2001, Pages 22-32

  Zhang, Zhao ^a   Zhu, Zhichun ^a   Zhang, Xiaodong ^a  

^a The College of William and Mary   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DATA TRANSFER; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; PROGRAM PROCESSORS;

INSTRUCTION LEVEL PARALLELISM PROCESSORS (ILP);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035389657     PISSN: 02721732     EISSN: None     Source Type: Journal    
DOI: 10.1109/40.946676     Document Type: Article

References (11)

1. Memory bandwidth limitations of future microprocessors
2. A performance comparison of contemporary DRAM architectures
3. Performance of cached DRAM organizations in vector supercomputers
4. The cache DRAM architecture: A DRAM with an on-chip cache memory
5. CDRAM in a unified memory architecture
6. Trends in semiconductor memories
7. A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality
8. Reducing DRAM latencies with an integrated memory hierarchy design