Staged reads: Mitigating the impact of DRAM writes on DRAM reads

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 41-52

  Chatterjee, Niladrish ^a   Muralimanohar, Naveen ^b   Balasubramonian, Rajeev ^a   Davis, Al ^a   Jouppi, Norman P ^b  

^a UNIVERSITY OF UTAH   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; CRITICAL PATHS; I/O PADS; MAIN MEMORY; MEMORY CHANNELS; MEMORY CHIPS; MEMORY SYSTEMS; OFF-CHIP MEMORIES; PREFETCHES; READ OPERATION; SINGLE CHANNELS; THROUGHPUT IMPROVEMENT; WRITE-INTENSIVE WORKLOADS;

BUSES; COMPUTER ARCHITECTURE; SUPERCOMPUTERS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84860350704     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168943     Document Type: Conference Paper

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