SIMD defragmenter: Efficient ILP realization on data-parallel architectures

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2012, Pages 363-374

  Park, Yongjun ^a   Seo, Sangwon ^a,b   Park, Hyunchul ^a,c   Cho, Hyoun Kyu ^a   Mahlke, Scott ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b QUALCOMM INC   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

compiler; optimization; SIMD architecture

Indexed keywords

AUTOMATIC VECTORIZATION; COMPILER; COMPLEX CONTROL FLOW; DATA PACKING; DATA-LEVEL PARALLELISM; DATA-PARALLEL ARCHITECTURES; DE-FRAGMENTATION; ENERGY EFFICIENT; INSTRUCTION-LEVEL PARALLELISM; LOOP VECTORIZATION; MEDIA APPLICATION; MOBILE SYSTEMS; REAL APPLICATIONS; RESEARCH APPROACH; SCIENTIFIC APPLICATIONS; SIMD ARCHITECTURE; SINGLE-INSTRUCTION MULTIPLE-DATA; SUBGRAPHS; VECTORIZATION;

ARCHITECTURE; EMBEDDED SYSTEMS; OPTIMIZATION; PARALLEL ARCHITECTURES; PROBLEM ORIENTED LANGUAGES;

PROGRAM COMPILERS;

EID: 84863353689     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2150976.2151014     Document Type: Conference Paper

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