SODA: A low-power architecture for software radio

Proceedings - International Symposium on Computer Architecture

Volumn 2006, Issue , 2006, Pages 89-100

  Lin, Yuan ^a   Lee, Hyunseok ^a   Woh, Mark ^a   Harel, Yoav ^a   Mahlke, Scott ^a   Mudge, Trevor ^a   Chakrabarti, Chaitali ^b   Flautner, Krisztián ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Arizona State University   (United States)

^c ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER ARCHITECTURE; POWER CONSUMPTION; PROGRAMMABLE HARDWARE PLATFORMS; SOFTWARE RADIO;

COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; WIRELESS TELECOMMUNICATION SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 33845875162     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2006.37     Document Type: Conference Paper

References (26)

1. ANSI/IEEE Std 802.11, 1999 Edition, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications.
2. ARM Cortex-M3: http://www.arm.com/products/CPUs/ARM-Cortex-M3.html.
3. DSP Developers' Village, Texas Instruments: http://dspvillage.ti.com.
4. Predictive Technology Model: http://www.eas.asu.edu/ptm/.
5. QuickSilver Technology: http://www.qstech.com/.
6. J. H. Ahn et al. Evaluating the Imagine Stream Architecture. In Proceedings of the 31st Annual International Symposium on Computer Architecture, June 2004.
7. R. Baines and D. Pulley. Software defined baseband processing for 3G base stations. In 4th International Conference on 3G Mobile Communication Technologies (Conf. Publ. No. 494), pages 123-127, June 2003.
8. I. Chen, A. Chun, E. Tsui, H. Honary, and V. Tsai. Overview of Intel's Reconfigurable Communication Architecture. In 3rd Workshop on Application Specific Processors, pages 95-102, Sept. 2004.
9. Cray Research Inc. The Cray-1 Computer System, Publication No.2240008b 1976.
10. D. E. Culler, J. P. Singh, and A. Gupta. Parallel Computer Architecture: A Hardware/Software Approach. Morgan Kaufmann Publishers, Inc., San Francisco, California, 1999.
11. K. Diefendorff, P. Dubey, R. Hochsprung, and H. Scales. AltiVec Extension to PowerPC Accelerates Media. Processing. In IEEE Micro, volume 20, no. 2, pages 85-95, Mar./Apr. 2000.
12. J. Glossner, E. Hokenek, and M. Moudgill. The Sandbridge Sandblaster Communications Processor. In 3rd Workshop on Application Specific Processors, pages 53-58, Sept. 2004.
13. P. H. Hofstee. All About the Cell Processor. In IEEE Symposium on Low-Power and High-Speed Chips(COOL Chips VIII), April 2005.
14. H. Holma and A. Toskala. WCDMA for UMTS: Radio Access For Third Generation Mobile Communications. John Wiley and Sons, LTD, New York, New York, 2001.
15. H. C. Hunter and J. H. Moreno. A New Look at Exploiting Data Parallelism in Embedded System. In Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, pages 159-169, 2003.
16. C. Kozyrakis and D. Patterson. Vector Vs. Superscalar and VLIW Architectures for Embedded Multimedia. Benchmarks. In Proceedings of the 35th Annual ACM/IEEE International Symposium on Microarchitecture, pages 283-293, Nov. 2002.
17. C. Kozyrakis and D. Patterson. Overcoming the Limitations of Conventional Vector Processors. In Proceedings of the 30th Annual International Symposium on Computer Architecture, pages 399-409, 2003.
18. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communicatons Systems. In Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, pages 330-335, 1997.
19. H. Lee et al. Software Defined Radio - A High Performance Embedded Challenge. In Proc. 2005 Intl. Conference on High Performance Embedded Architectures and Compilers (HiPEAC), Nov. 2005.
20. A. Lodi et al. XiSystem: A XiRisc-Based SoC With Reconfigurable IO Module. In IEEE Journal of Solid-State Circuits, volume 41, No. 1, pages 85-96, Jan. 2006.
21. Y. Neuvo. Cellular Phones as Embedded Systems. In IEEE International Solid-State Circuits Conference, 2004.
22. A. Peleg and U. Weiser. MMX Technology Extension to the Intel Architecture. In IEEE Micro, volume 16, no. 4, Aug. 1996.
23. S. Rixner et al. Register Organization for Media Processing. In Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, pages 375-386, Jan. 2000.
24. H. Stone. Parallel Processing with the Perfect Shuffle. In IEEE Transactions on Computers, volume 20, Feb.
25. C. van Berkel et al. Vector Processing as an Enabler for Software-Defined Radio in Handsets From 3G+WLAN Onwards. In Proc. 2004 Software Defined Radio Technical Conference, Nov. 2004.
26. A. Waksman. A Permutation Network. In Journal of the ACM, volume 15, No. 1, pages 159-163, Jan. 1968.