Efficient selection of vector instructions using dynamic programming

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2010, Pages 201-212

  Barik, Rajkishore ^a   Zhao, Jisheng ^b   Sarkar, Vivek ^b  

^a INTEL CORPORATION   (United States)

^b RICE UNIVERSITY   (United States)

Author keywords

Dynamic optimization; Dynamic programming; Instruction selection; Vectorization

Indexed keywords

ALGEBRAIC SIMPLIFICATION; ALLOCATORS; COMPILE TIME; DYNAMIC COMPILATION; DYNAMIC COMPILER; DYNAMIC OPTIMIZATION; EMBEDDED APPLICATION; FORTRAN COMPILERS; INSTRUCTION SCHEDULER; INSTRUCTION SELECTION; INSTRUCTION SELECTION ALGORITHM; LINE CODES; MODERN PROCESSORS; NUMERICAL BENCHMARK; OPEN-SOURCE; PARALLELIZATIONS; PERFORMANCE IMPROVEMENTS; PROGRAM PERFORMANCE; SIMD INSTRUCTIONS; VECTOR OPERATIONS; VECTORIZATION; XEON PROCESSORS;

ALGEBRA; ALGORITHMS; MULTIMEDIA SYSTEMS; OPTIMIZATION; PROGRAM COMPILERS; VECTORS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

DYNAMIC PROGRAMMING;

EID: 79951702599     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2010.38     Document Type: Conference Paper

References (28)

1. Jikes RVM. http://jikesrvm.org/.
2. GCC compiler. http://gcc.gnu.org/, 2004.
3. A. V. Aho and S. C. Johnson. Optimal code generation for expression trees. In STOC '75: Proceedings of seventh annual ACM symposium on Theory of computing, pages 207-217, New York, NY, USA, 1975. ACM.
4. Intel Advanced Vector Extensions Programming Reference., 2008. Available at http://softwarecommunity.intel.com/isn/downloads/intelavx/Intel-AVX- Programming-Reference-31943302.pdf/.
5. Aart J. C. Bik. Applying Multimedia Extensions for Maximum Performance. Intel Press., 2004.
6. John Bruno and Ravi Sethi. Code generation for a one-register machine. J. ACM, 23(3):502-510, 1976.
7. Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, and Hunter Scales. Altivec extension to powerpc accelerates media processing. IEEE Micro, 20(2):85-95, 2000. (Pubitemid 30585387)
8. Alexandre E. Eichenberger, Peng Wu, and Kevin O'Brien. Vectorization for SIMD architectures with alignment constraints. SIGPLAN Not., 39(6):82-93, 2004.
9. D. H. Bailey et al. The NAS parallel benchmarks, 1994.
10. M.G. Burke et. al. The Jalapeño Dynamic Optimizing Compiler for Java. In ACM Java Grande Conference, June 1999.
11. Free Software Foundation. Auto-vectorization in GCC. GCC, 2004.
12. Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference, 1997. Available at http://developer.intel.com/design/PentiumII/ manuals/.
13. The Java Grande Forum benchmark suite. http://www.epcc.ed.ac.uk/ javagrande/javag.html.
14. Ken Kennedy and John R. Allen. Optimizing compilers for modern architectures: a dependence-based approach. Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, 2002.
15. David Ryan Koes and Seth Copen Goldstein. Near-optimal instruction selection on dags. In CGO '08, pages 45-54, New York, NY, USA, 2008. (Pubitemid 351667251)
16. S. Kral. FFT Specific Compilation on IBM Blue Gene. PhD thesis, Vienna University of Technology, June 2006.
17. S. Kral, F. Franchetti, J. Lorenz, and C. W. Ueberhuber. Fft compiler techniques. In Proceedings of International Conference on Compiler Construction (CC) 2004, pages 217-231. LNCS.
18. Andreas Krall and Sylvain Lelait. Compilation techniques for multimedia processors. Int. J. Parallel Program., 28(4):347-361, 2000.
19. Alexei Kudriavtsev and Peter Kogge. Generation of permutations for SIMD processors. In LCTES '05, pages 147-156, New York, NY, USA, 2005. ACM.
20. Samuel Larsen and Saman Amarasinghe. Exploiting superword level parallelism with multimedia instruction sets. In PLDI '00: Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation, pages 145-156, New York, NY, USA, 2000. ACM Press. (Pubitemid 32394090)
21. Samuel Larsen, Rodric Rabbah, and Saman Amarasinghe. Exploiting vector parallelism in software pipelined loops. In MICRO 38, pages 119-129, Washington, DC, USA, 2005. IEEE Computer Society.
22. Samuel Larsen, Emmett Witchel, and Saman Amarasinghe. Increasing and detecting memory address congruence. In In International Conference on Parallel Architectures and Compilation Techniques, pages 18-29, 2002.
23. Bachega et. al. Leonardo. A high-performance SIMD floating point unit for Bluegene/L: Architecture, compilation, and algorithm design. In PACT '04, pages 85-96, Washington, DC, USA, 2004. IEEE Computer Society.
24. Rainer Leupers. Code selection for media processors with SIMD instructions, 2000.
25. Alex Peleg and Uri Weiser. MMX technology extension to the intel architecture. IEEE Micro, 16(4):42-50, 1996. (Pubitemid 126534429)
26. Ivan Pryanishnikov, Andreas Krall, and Nigel Horspool. Compiler optimizations for processors with SIMD instructions. Software - Practice and Experience, 37(1):93-113, 2007. (Pubitemid 46133006)
27. Vivek Sarkar, Mauricio J. Serrano, and Barbara B. Simons. Registersensitive selection, duplication, and sequencing of instructions. In ICS '01: Proceedings of the 15th international conference on Supercomputing, pages 277-288, New York, NY, USA, 2001. (Pubitemid 32865323)
28. R. Vallée-Rai et al. SOOT - a Java Optimization Framework. In Proceedings of CASCON 1999, pages 125-135, 1999.