Global register partitioning

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2000, Pages 13-23

  Hiser, Jason ^a   Carr, Steve ^b   Sweany, Philip ^b  

^a University of Virginia   (United States)

^b Michigan Technological University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; RESOURCE ALLOCATION; SCHEDULING; SHIFT REGISTERS;

GLOBAL REGISTER PARTITIONING; INSTRUCTION LEVEL PARALLELISM; MONOLITHIC REGISTER BANK; REGISTER ALLOCATION METHODS;

COMPUTER ARCHITECTURE;

EID: 0034499080     PISSN: 1089795X     EISSN: None     Source Type: Journal    
DOI: 10.1109/PACT.2000.888256     Document Type: Article

References (12)

1. S. Beaty S. Colcord P. Sweany Using genetic algorithms to fine-tune instruction scheduling Proceedings of the Second International Conference on Massively Parallel Computing Systems Proceedings of the Second International Conference on Massively Parallel Computing Systems Ischia Italy 1996-May
2. A. Capitanio N. Dutt A. Nicolau Partitioned Register Files for VLIW's: A Preliminary Analysis of Tradeoffs Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO-25) 292 300 Proceedings of the 25th Annual International Symposium on Microarchitecture (MICRO-25) Portland OR 1992-December-1-4
3. G. J. Chaitin Register allocation and spilling via graph coloring Proceedings of the ACM SIGPLAN '82 Symposium on Compiler Construction 98 105 Proceedings of the ACM SIGPLAN '82 Symposium on Compiler Construction Boston MA 1982-June
4. G. Desoli Instruction assignment for clustered VLIW DSP compilers: A new approach Jan. 1998 HPL-98-13 HP Labs
5. J. R. Ellis A Compiler for VLIW Architectures 1984 Yale University
6. J. Hiser S. Carr P. Sweany Register Assignment for Software Pipelining with Partitioned Register Banks International Parallel and Distributed Processing Symposium (IPDPS 2000) 211 217 International Parallel and Distributed Processing Symposium (IPDPS 2000) 2000-May
7. S. Jang S. Carr P. Sweany D. Kuras A code generation framework for VLIW architectures with partitioned register files Proceedings of the Third International Conference on Massively Parallel Computing Systems (MPCS) 61 69 Proceedings of the Third International Conference on Massively Parallel Computing Systems (MPCS) 1998-April
8. C. Lee C. Park M. Kim An efficient algorithm for graph partitioning using a problem transformation method Computer-Aided Design 611 619 July 1993
9. E. Nystrom A. Eichenberger Effective cluster assignment for modulo scheduling Proceedings of the 31 International Symposium on Microarchitecture (MICRO-31) 103 114 Proceedings of the 31 International Symposium on Microarchitecture (MICRO-31) Dallas TX 1998-December
10. E. Ozer S. Banerjia T. Conte Unified assign and schedule: A new approach to scheduling for clustered register file microarchitectures Proceedings of the 31st International Symposium on Microarchitecture (MICRO-31) 308 316 Proceedings of the 31st International Symposium on Microarchitecture (MICRO-31) Dallas TX 1998-December
11. P. H. Sweany S. J. Beaty Overview of the Rocket retargetable C compiler January 1994 Houghton CS-94-01 Department of Computer Science, Michigan Technological University
12. Details on Signal Processing 47 March 1997 Texas Instruments