Edge-centric modulo scheduling for coarse-grained reconfigurable architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2008, Pages 166-176

  Park, Hyunchul ^a   Fan, Kevin ^a   Mahlke, Scott ^a   Oh, Taewook ^b   Kim, Heeseok ^b   Kim, Hong Seok ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

Author keywords

Coarse grained Reconfigurable Architecture; Operand Routing; Programmable Accelerator; Software Pipelining

Indexed keywords

COARSE-GRAINED RECONFIGURABLE ARCHITECTURE; COMPILER SCHEDULING; COST METRICS; DATA-FLOW GRAPHS; DIMENSIONAL GRIDS; FUNCTION UNITS; GLOBAL PERSPECTIVES; GUIDE SELECTIONS; HARDWARE PLATFORMS; LOW COSTS; MODULO SCHEDULING; OPERAND ROUTING; PRIMARY OBJECTIVES; PROGRAMMABLE ACCELERATOR; REGISTER FILES; ROUTING PROBLEMS; ROUTING PROCESS; SIMULATED ANNEALING TECHNIQUES; SOFTWARE IMPLEMENTATIONS; SOFTWARE PIPELINING; TIME AND SPACES;

DATA FLOW ANALYSIS; DECODING; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; MAGNETIC SUSCEPTIBILITY; PARALLEL ARCHITECTURES; PROGRAM PROCESSORS; SIMULATED ANNEALING;

SCHEDULING;

EID: 63549126166     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1454115.1454140     Document Type: Conference Paper

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