An architecture framework for transparent instruction set customization in embedded processors

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2005, Pages 272-283

  Clark, Nathan ^a   Blome, Jason ^a   Chu, Michael ^a   Mahlke, Scott ^a   Biles, Stuart ^b   Flautner, Krisztián ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b ARM LTD   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; GRAPH THEORY; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS;

DATAFLOWS; INSTRUCTION SET CUSTOMIZATION; LATENCY; PLUG-AND-PLAY MODEL;

COMPUTER ARCHITECTURE;

EID: 27544482359     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1080695.1069993     Document Type: Conference Paper

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