Compiler-controlled caching in superword register files for multimedia extension architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn 2002-January, Issue , 2002, Pages 45-55

  Shin, Jaewook ^a   Chame, J ^a   Hall, M W ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

Aggregates; Bandwidth; Computer aided instruction; Computer architecture; Delay; Instruction sets; Multimedia computing; Optimizing compilers; Parallel processing; Registers

Indexed keywords

AGGREGATES; ALGORITHMS; BANDWIDTH; CACHE MEMORY; COMPUTER AIDED INSTRUCTION; COMPUTER ARCHITECTURE; MEMORY ARCHITECTURE; PARALLEL ARCHITECTURES;

DELAY; INSTRUCTION SET; MULTIMEDIA COMPUTING; OPTIMIZING COMPILERS; PARALLEL PROCESSING; REGISTERS;

PROGRAM COMPILERS;

EID: 84948740064     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2002.1106003     Document Type: Conference Paper

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