Opportunities and challenges of using plasmonic components in nanophotonic architectures

IEEE Journal on Emerging and Selected Topics in Circuits and Systems

Volumn 2, Issue 2, 2012, Pages 154-168

  Wassel, Hassan M G ^a   Dai, Daoxin ^b   Tiwari, Mohit ^c   Valamehr, Jonathan K ^a   Theogarajan, Luke ^a   Dionne, Jennifer ^d   Chong, Frederic T ^a   Sherwood, Timothy ^a  

^a University of California   (United States)

^b ZHEJIANG UNIVERSITY   (China)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d Stanford University   (United States)

Author keywords

Energy efficient network on chip; nanophotonics; on chip interconnects; plasmonics

Indexed keywords

ENERGY COST; HIGH BANDWIDTH; HYBRID CHANNELS; HYBRID SCHEME; LOW LATENCY; MICRORING RESONATOR; NETWORK ON CHIP; NETWORK-ON-CHIPS; ON-CHIP INTERCONNECTS; PLASMONIC; PLASMONIC DEVICES; PLASMONICS; POWER EFFICIENCY; PROCESS VARIATION; PROPAGATION LOSS; TEMPERATURE DEPENDENCE; WAVE-GUIDING;

NANOPHOTONICS; OPTICAL RESONATORS; ROUTERS; VLSI CIRCUITS;

PLASMONS;

EID: 84862309855     PISSN: 21563357     EISSN: None     Source Type: Journal    
DOI: 10.1109/JETCAS.2012.2193934     Document Type: Article

References (49)

1. H. A. Atwater, "The promise of plasmonics," Sci. Am., vol. 296, no. 4, pp. 56-63, April 2007.
2. J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. 20th Annu. Int. Conf. Supercomput., 2006, pp. 187-198, ACM. (Pubitemid 47168505)
3. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. W. Holzwarth, M. A. Popovic, H. Li, H. I. Smith, J. L. Hoyt, F. X. Kartner, R. J. Ram, V. Stojanovic, and K. Asanovic, "Building many-core processor-to-dram networks with monolithic CMOS silicon photonics," IEEE Micro, vol. 29, no. 4, pp. 8-21, 2009.
4. S. Beamer, C. Sun, Y.-J. Kwon, A. Joshi, C. Batten, V. Stojanovi, and K. Asanovi, "Re-architecting dram memory systems with monolithi-cally integrated silicon photonics," SIGARCH Comput. Archit. News, vol. 38, no. 3, pp. 129-140, 2010.
5. A. Biberman, N. Sherwood-Droz, X. Zhu, M. Lipson, and K. Bergman, "High-speed data transmission in multi-layer deposited silicon photonics for advanced photonic networks-on-chip," in CLEO'11, 2011, pp. 1-2.
6. M. Brongersma, personal communication, 2010.
7. W. Cai, J. White, and M. Brongersma, "Compact, high-speed and power-efficient electrooptic plasmonic modulators," Nano Lett., vol. 9, no. 12, pp. 4403-4411, 2009.
8. M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi, "Phastlane: A rapid transit optical routing network," in Proc. 36th Annu. Int. Symp. Comput. Arch., 2009, pp. 441-450, ACM.
9. W. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Francisco, CA: Morgan Kaufmann, 2003.
10. C. Delacour, S. Blaize, P. Grosse, J. M. Fedeli, A. Bruyant, R. Salas-Montiel, G. Lerondel, and A. Chelnokov, "Efficient directional coupling between silicon and copper plasmonic nanoslot waveguides: Toward metaloxidesilicon nanophotonics," Nano Lett., vol. 10, no. 8, pp. 2922-2926, 2010.
11. C. T. DeRose, M. R. Watts, D. C. Trotter, D. L. Luck, G. N. Nielson, and R. W. Young, "Silicon microring modulator with integrated heater and temperature sensor for thermal control," in Lasers Electro-Optics (CLEO) Quantum Electron. Laser Sci. Conf. (QELS), May 2010, pp. 1-2.
12. J. Dionne, L. Sweatlock, M. Sheldon, A. Alivisatos, and H. Atwater, "Silicon-based plasmonics for on-chip photonics," IEEE J. Sel. Topics Quantum Electron., vol. 16, no. 1, pp. 295-306, Jan.-Feb. 2010.
13. J. A. Dionne, K. Diest, L. A. Sweatlock, and H. A. Atwater, "Plas-mostor: A metal-oxide-si field effect plasmonic modulator," Nano Lett., vol. 9, no. 2, pp. 897-902, Jan. 2009.
14. J. A. Dionne, L. A. Sweatlock, H. A. Atwater, and A. Polman, "Plasmon slot waveguides: Towards chip-scale propagation with subwavelength-scale localization," Phys. Rev. B, vol. 73, no. 3, p. 035407, 2006.
15. P. Dong, S. Liao, D. Feng, H. Liang, D. Zheng, R. Shafiiha, C.-C. Kung, W. Qian, G. Li, X. Zheng, A. V. Krishnamoorthy, and M. Asghari, "Low vpp, ultralow-energy, compact, high-speed silicon electro-optic modulator," Opt. Exp., vol. 17, no. 25, pp. 22484-22490, Dec. 2009.
16. M. Fiorentino, IEEE Photon. Soc. 22nd Annu. Workshop Interconnections High Speed Digital Syst. Santa Fe, NM, 2011.
17. M. Georgas, J. Leu, B. Moss, C. Sun, and V. Stojanovic, "Addressing link-level design tradeoffs for integrated photonic interconnects," in IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2011, pp. 1-8.
18. J. Grandidier, G. C. des Francs, S. Massenot, A. Bouhelier, L. Markey, J.-C. Weeber, C. Finot, and A. Dereux, "Gain-assisted propagation in a plasmonic waveguide at telecom wavelength," Nano Lett., vol. 9, no. 8, pp. 2935-2939, Aug. 2009.
19. B. Guha, B. B. C. Kyotoku, and M. Lipson, "CMOS-compatible athermal silicon microring resonators," Opt. Exp., vol. 18, no. 4, pp. 3487-3493, Feb. 2010.
20. A. Joshi, C. Batten, Y.-J. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic, "Silicon-photonic clos networks for global on-chip communication," in Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, NOCS '09.
21. J. Kim, J. Balfour, and W. Dally, "Flattened butterfly topology for on-chip networks," in Proc. 40th Annu. IEEE/ACM Int. Symp. Microarchitecture, 2007, pp. 172-182.
22. J. Kim, W. J. Dally, and D. Abts, "Flattened butterfly: A cost-efficient topology for high-radix networks," in Proc. 34th Annu. Int. Symp. Comput. Architecture, New York, 2007, pp. 126-137. (Pubitemid 47582097)
23. J. Kim, W. J. Dally, S. Scott, and D. Abts, "Technology-driven, highly-scalable dragonfly topology," in Proc. 35th Annu. Int. Symp. Comput. Architecture, 2008, pp. 77-88.
24. N. Kirman, M. Kirman, R. K. Dokania, J. F. Martínez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi, "Leveraging optical technology in future bus-based chip multiprocessors," in Proc. 39th Annu. IEEE/ACM Int. Symp. Microarchitecture, 2006, pp. 492-503. (Pubitemid 351337021)
25. N. Kirman and J. F. Martínez, "A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing," in Proc. 15th Ed. ASPLOS Architectural Support Programm. Languages Operat. Syst., 2010, pp. 15-28.
26. P. Koka, M. O. McCracken, H. Schwetman, X. Zheng, R. Ho, and A. V. Krishnamoorthy, "Silicon-photonic network architectures for scalable, power-efficient multi-chip systems," in Proc. 37th Annu. Int. Symp. Comput. Architecture, 2010, pp. 117-128.
27. S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen, and N. P. Jouppi, "Mcpat: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchitecture, 2009, pp. 469-480.
28. Z. Li, M. Mohamed, X. Chen, E. Dudley, K. Meng, L. Shang, A. Mick-elson, R. Joseph, M. Vachharajani, B. Schwartz, and Y. Sun, "Reliability modeling and management of nanophotonic on-chip networks," IEEE Trans. Very Large Scale (VLSI) Syst., vol. 20, no. 1, pp. 98-111, Jan. 2012.
29. K. MacDonald and N. Zheludev, "Active plasmonics: Current status," Laser Photon. Rev., vol. 4, no. 4, pp. 562-567, 2010.
30. N. McKeown, "The islip scheduling algorithm for input-queued switches," IEEE/ACM Trans. Netw., vol. 7, no. 2, pp. 188-201, Apr. 1999.
31. F. J. Mesa-Martinez, E. K. Ardestani, and J. Renau, "Characterizing processor thermal behavior," in Proc. 15th Ed. ASPLOS Architectural Support Programm. Languages Operat. Syst., 2010.
32. T. Nikolajsen, K. Leosson, and S. I. Bozhevolnyi, "Surface plasmon polariton based modulators and switches operating at telecom wavelengths," Appl. Phys. Lett., vol. 85, no. 24, pp. 5833-5835, 2004. (Pubitemid 40817912)
33. C. Nitta, M. Farrens, and V. Akella, "Addressing system-level trimming issues in on-chip nanophotonic networks," in IEEE 17th Int. Symp. High Performance Comput. Architecture (HPCA), Feb. 2011.
34. J. S. Orcutt, A. Khilo, C. W. Holzwarth, M. A. Popovi, H. Li, J. Sun,T. Bonifield, R. Hollingsworth, F. X. Kärtner, H. I. Smith, V. Stojanovi, and R. J. Ram, "Nanophotonic integration in state-of-the-art CMOS foundries," Opt. Exp., vol. 19, no. 3, pp. 2335-2346, Jan. 2011.
35. D. Pacifici, H. J. Lezec, and H. A. Atwater, "All-optical modulation by plasmonic excitation of CDSE quantum dots," Nature Photon., vol. 1, no. 7, pp. 402-406, July 2007.
36. Y. Pan, J. Kim, and G. Memik, "Flexishare: Energy-efficient nanopho-tonic crossbar architecture through channel sharing," in IEEE Int. Symp. High Performance Comput. Architecture (HPCA), 2010, pp. 1-12.
37. Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary, "Firefly: Illuminating future network-on-chip with nanophotonics," in Proc. 36th Annu. Int. Symp. Comput. Architecture, 2009, pp. 429-440.
38. G. T. Reed, G. Mashanovich, F. Y. Gardes, and D. J. Thomson, "Silicon optical modulators," Nature Photon., vol. 4, no. 8, pp. 518-526, Jul. 2010.
39. D. Sanchez, G. Michelogiannakis, and C. Kozyrakis, "An analysis of on-chip interconnection networks for large-scale chip multiprocessors," ACM Trans. Archit. Code Optim., vol. 7, no. 1, pp. 1-28, 2010.
40. A. Shacham, K. Bergman, and L. Carloni, "Photonic networks-on-chip for future generations of chip multiprocessors," IEEE Trans. Comput., vol. 57, no. 9, pp. 1246-1260, Sep. 2008.
41. N. Sherwood-Droz, K. Preston, J. S. Levy, and M. Lipson, "Device guidelines for wdm interconnects using silicon microring resonators," in Workshop on the Interaction Between Nanophotonic Devices Syst. (WINDS 2010), Dec. 2010, pp. 15-17.
42. D. Vantrease, N. Binkert, R. Schreiber, and M. H. Lipasti, "Light speed arbitration and flow control for nanophotonic interconnects," in Proc. 42nd Annu. IEEE/ACM Int. Symp. Microarchitecture, 2009, pp. 304-315.
43. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn, "Corona: System implications of emerging nanophotonic technology," in Proc. 35th Annu. Int. Symp. Comput. Architecture, 2008.
44. G. Veronis and S. Fan, "Theoretical investigation of compact couplers between dielectric slabwaveguides and two-dimensional metal-dielectric-metal plasmonicwaveguides," Opt. Exp., vol. 15, no. 3, pp. 153-164, 2007.
45. Q. Xu, D. Fattal, and R. G. Beausoleil, "Silicon microring resonators with 1.5-radius," Opt. Exp., vol. 16, no. 6, pp. 4309-4315, Mar. 2008.
46. Q. Xu, S. Manipatruni, B. Schmidt, J. Shakya, and M. Lipson, "12.5 gbit/s carrier-injection-based silicon micro-ring silicon modulators," Opt. Exp., vol. 15, no. 2, pp. 430-436, Jan. 2007. (Pubitemid 46168487)
47. L. Zhou, K. Okamoto, and S. Yoo, "Athermalizing and trimming of slotted silicon microring resonators with uv-sensitive pmma upper-cladding, " IEEE Photon. Technol. Lett., vol. 21, no. 17, pp. 1175-1177, Sep. 2009.
48. R. Zia, M. D. Selker, P. B. Catrysse, and M. L. Brongersma, "Geometries and materials for subwavelength surface plasmon modes," J. Opt. Soc. Am. A, vol. 21, no. 12, pp. 2442-2446, 2004. (Pubitemid 40009341)
49. W. A. Zortman, D. C. Trotter, and M. R. Watts, "Silicon photonics manufacturing," Opt. Exp., vol. 18, no. 23, pp. 23598-23607, Nov. 2010.