Reliability modeling and management of nanophotonic on-chip networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 1, 2012, Pages 98-111

  Li, Zheng ^a   Mohamed, Moustafa ^b   Chen, Xi ^b   Dudley, Eric ^b   Meng, Ke ^c   Shang, Li ^b   Mickelson, Alan R ^b   Joseph, Russ ^c   Vachharajani, Manish ^b   Schwartz, Brian ^d   Sun, Yihe ^a  

^a TSINGHUA UNIVERSITY   (China)

^b University of Colorado at Boulder   (United States)

^c Northwestern University   (United States)

^d TECH X CORPORATION   (United States)

Author keywords

Multicore processing; Multiprocessor interconnection networks; Nanophotonics; Reliability

Indexed keywords

ELECTRICAL INTERCONNECTS; MANY-CORE; MULTIPROCESSOR INTERCONNECTIONS; NANOPHOTONIC STRUCTURES; ON CHIPS; ON-CHIP NETWORKS; PROCESS VARIATION; RELIABILITY MODELING; RUNTIMES; SENSITIVITY TO VARIATIONS; SYSTEM INTEGRATION; SYSTEM LEVELS; THERMAL VARIATION; TRANSISTOR PERFORMANCE;

EMBEDDED SYSTEMS; ENERGY EFFICIENCY; INTERCONNECTION NETWORKS; RELIABILITY; SENSITIVITY ANALYSIS;

NANOPHOTONICS;

EID: 83655164004     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2010.2089072     Document Type: Article

References (39)

1. R. G. Beausoleil et al. , "Nanoelectronic and nanophotonic interconnect, " Proc. IEEE, vol. 96, no. 2, pp. 230-247, Feb. 2008.
2. A. Shacham, K. Bergman, and L. Carloni, "Photonic networks-onchip for future generations of chip multiprocessors, " IEEE Trans. Computers, vol. 57, no. 9, pp. 1246-1260, Sep. 2008.
3. D. Vantrease et al. , "Corona: System implications of emerging nanophotonic technology, " in Proc. Int. Symp. Comput. Architect. , 2008, pp. 153-164.
4. A. Joshi et al. , "Silicon-photonic clos networks for global on-chip communication, " in Proc. Int. Symp. Networks-on-Chip, May 2009, pp. 124-133.
5. Y. Pan et al. , "Firefly: Illuminating future network-on-chip with nanophotonics, " in Proc. Int. Symp. Comput. Architect. , Jun. 2009, pp. 429-440.
6. R. K. Dokania and A. B. Apsel, "Analysis of challenges for on-chip optical interconnects, " in Proc. Great Lakes Symp. VLSI, 2009, pp. 275-280.
7. Q. Xu et al. , "12. 5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators, " Opt. Express, vol. 15, no. 2, pp. 430-436, 2007. (Pubitemid 46168487)
8. J. K. S. Poon et al. , "Wide-range tuning of polymer microring resonators by the photobleaching of the CLD-1 chromophores, " Opt. Lett. , vol. 29, no. 22, pp. 2584-2586, 2004.
9. M. R. Watts et al. , "Ultralow power silicon microdisk modulators and switches, " in IEEE Int. Conf. on Group IV Photonics, Sep. 2008, p. 4.
10. M. A. Popovic, "Theory and design of high-index-contrast microphotonic circuits, " Ph. D. dissertation, MIT, Cambridge, 2008.
11. G. Roelkens et al. , "III-V/silicon photonics for on-chip and intra-chip optical interconnects, " Laser Photon. Rev. , vol. 4, no. 6, pp. 751-779, 2010.
12. D. Liang et al. , "Hybrid integrated platforms for silicon photonics, " Materials, vol. 3, no. 3, pp. 1782-1802, 2010.
13. ePIXfab [Online]. Available: http://www.epixfab. eu/
14. S. Manipatruni et al. , "Wide temperature range operation of micrometerscale silicon electro-optic modulators, " Opt. Lett. , vol. 33, no. 19, pp. 2185-2187, 2008.
15. Q. Li et al. , "Design and demonstration of compact, wide bandwidth coupled-resonator filters on a siliconon-insulator platform, " Opt. Express, vol. 17, no. 4, pp. 2247-2254, 2009.
16. B. E. A. Saleh and M. C. Teich, Fundamentals of Photonics, 2nd ed. Hoboken, NJ: Wiley, 2007.
17. G. P. Agrawal, Fiber-Optic Communication Systems. Hoboken, NJ: Wiley, 2002.
18. H. K. Tsang et al. , "Optical dispersion, two-photon absorption and selfphase modulation in silicon waveguides at 1. 5 m wavelength, " Appl. Phys. Lett. , vol. 80, no. 3, pp. 416-418, Jan. 2002.
19. M. A. Popovic, "Theory and design of high-index-contrast microphotonic circuits, " Ph. D. dissertation, MIT, Cambridge, 2008.
20. C. Holzwarth et al. , "Localized substrate removal technique enabling strong-confinement microphotonics in bulk si cmos processes, " in Conf. Lasers and Electro-Optics and Conf. on Quantum Electron. Laser Sci. . (CLEO/QELS), May 2008, pp. 1-2.
21. B. Guha, B. B. C. Kyotoku, and M. Lipson, "Cmos-compatible athermal silicon microring resonators, " Opt. Express, vol. 18, no. 4, pp. 3487-3493, 2010.
22. Z. Hassan et al. , "Multiscale thermal analysis for nanometer-scale integrated circuits, " IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , vol. 28, no. 6, pp. 860-873, Jun. 2009.
23. R. Soref and B. Bennett, "Electrooptical effects in silicon, " IEEE J Quantum Electron. , vol. QE-23, no. 1, pp. 123-129, Jan. 1987.
24. C. Zhu et al. , "Three-dimensional chip-multiprocessor run-time thermal management, " IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , vol. 27, no. 8, pp. 1479-1492, Aug. 2008.
25. C. Isci and M. Martonosi, "Runtime power monitoring in high-end processors: Methodology and empirical data, " in Proc. Int. Symp. Microarchitect. , Dec. 2003, pp. 93-104.
26. A. Kumar et al. , "HybDTM: A coordinated hardware-software approach for dynamic thermal management, " in Proc. Des. Autom. Conf. , Jul. 2006, pp. 548-553. (Pubitemid 47113957)
27. M. S. Floyd et al. , "System power management support in the IBM POWER6 microprocessor, " IBM J. Res. Develop. , vol. 51, no. 6, pp. 733-746, 2007.
28. D. Wendel et al. , "The implementation of power7tm: A highly parallel and scalable multi-core high-end server processor, " in Proc. Int. Solid- State Circuits Conf. , Feb. 2010, pp. 102-103.
29. J. Howard et al. , "A 48-core IA-32 message-passing processor with DVFS in 45 nm CMOS, " in Proc. Int. Solid-State Circuits Conf. , Feb. 2010, pp. 108-109.
30. R. Jayaseelan and T. Mitra, "A hybrid local-global approach for multicore thermal management, " in Proc. Int. Conf. Comput.-Aided Des. , 2009, pp. 314-320.
31. D. Oh et al. , "The compatibility analysis of thread migration and DVFS in multi-core processor, " in Proc. Int. Symp. Quality of Electron. Des. , 2010, pp. 866-871.
32. N. L. Binkert et al. , "The M5 simulator: Modeling networked systems, " IEEE Micro, vol. 26, no. 4, pp. 52-60, 2006. (Pubitemid 46504889)
33. D. Brooks, V. Tiwari, and M. Martonosi, "Wattch: A framework for architectural- level power analysis and optimizations, " in Proc. Int. Symp. Computer Architect. , Jun. 2000, pp. 83-94.
34. Y. Yang et al. , "ISAC: Integrated space and time adaptive chip-package thermal analysis, " IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , vol. 26, no. 1, pp. 86-99, Jan. 2007.
35. C. Isci and M. Martonosi, "Runtime power monitoring in high-end processors: Methodology and empirical data, " in Proc. Int. Symp. Microarchitect. , 2003, pp. 93-104.
36. Z. Li et al. , "A high-performance low-power nanophotonic on-chip network, " in Proc. Int. Symp. Low Power Electronics & Design, Aug. 2009, pp. 291-294.
37. Z. Li et al. , "Global on-chip coordination at light speed, " IEEE Des. Test of Comput. , vol. 27, no. 4, pp. 54-67, July 2010.
38. A. W. Topol et al. , "Three-dimensional integrated circuits, " IBM J. Res. Develop. , vol. 4, pp. 491-506, 2006. (Pubitemid 44364166)
39. A. Charlesworth, "The SUN fireplane system interconnect, " in Proc. Supercomput. Conf. , 2001, pp. 7-7.