Addressing system-level trimming issues in on-chip nanophotonic networks

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2011, Pages 122-131

  Nitta, Christopher ^a   Farrens, Matthew ^a   Akella, Venkatesh ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

A-THERMAL; BASIC BUILDING BLOCK; CO-LOCATED; CURRENT INJECTIONS; DRIFT PROPERTIES; FIXED COST; MICRORING RESONATOR; NON-LINEAR RELATIONSHIPS; ON CHIPS; RESONANT WAVELENGTHS; SLIDING WINDOW SCHEMES; SYSTEM LEVELS; THERMAL RUNAWAYS;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; COST ACCOUNTING; HEATING; NANOPHOTONICS; NETWORK ARCHITECTURE; RESONATORS;

TRIMMING;

EID: 79955897352     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2011.5749722     Document Type: Conference Paper

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