Addressing link-level design tradeoffs for integrated photonic interconnects

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2011, Pages

  Georgas, Michael ^a   Leu, Jonathan ^a   Moss, Benjamin ^a   Sun, Chen ^a   Stojanović, Vladimir ^a  

^a USA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-TO-CHIP BANDWIDTH; CIRCUIT TECHNOLOGY; COMPONENT MODEL; DEGREE OF PARALLELISM; DESIGN SPACE EXPLORATION; DESIGN TRADEOFF; INTEGRATED PHOTONICS; MANY-CORE; ON CHIPS; PHOTONIC LINKS; POTENTIAL SOLUTIONS; RING RESONATOR;

DESIGN; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; OPTIMIZATION; PRINTED CIRCUIT DESIGN; SPACE RESEARCH;

INTEGRATION;

EID: 80455178650     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2011.6055363     Document Type: Conference Paper

References (24)

1. R. J. Riedlinger et al., "A 32nm 3.1 billion transistor 12-wide-issue Itanium; processor for mission-critical servers," in ISSCC '11, feb. 2011, pp. 84 -86.
2. S. Palermo et al., "A 90 nm CMOS 16 Gb/s transceiver for optical interconnects," JSSCC, vol. 43, no. 5, pp. 1235-1246, May 2008. (Pubitemid 351596354)
3. C. Batten et al., "Building manycore processor-to-dram networks with monolithic silicon photonics," HOTI '08, pp. 21-30, Aug. 2008.
4. G. Kurian et al., "ATAC: a 1000-core cache-coherent processor with on-chip optical network," in Proceedings of PACT '10. NewYork,NY, USA: ACM, 2010, pp. 477-488.
5. A. Joshi et al., "Silicon-photonic clos networks for global on-chip communication," in Proceedings of NoCS '09, may 2009, p. 91.
6. D. Vantrease et al., "Corona: System implications of emerging nanophotonic technology," in Proceedings of ISCA '08. Washington, DC, USA: IEEE Computer Society, 2008, pp. 153-164.
7. S. Beamer et al., "Re-architecting DRAM memory systems with monolithically integrated silicon photonics," in Proceedings of ISCA '10. New York, NY, USA: ACM, 2010, pp. 129-140.
8. R. Soref et al., "Electrooptical effects in silicon," IEEE Journal of Quantum Electronics, vol. 23, no. 1, January 1987.
9. Q. Xu et al., "12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators," Optical Society of America, vol. 15, no. 2, 2007.
10. M. Watts, D. Trotter, R. Young, and A. Lentine, "Maximally confined silicon microphotonic modulators and switches," in IEEE Lasers and Electro-Optics Society, 2008. LEOS 2008. 21st Annual Meeting of the, nov. 2008, pp. 457 -458.
11. K.-L. Wong et al., "Offset compensation in comparators with minimum input-referred supply noise," JSSCC, vol. 39, no. 5, pp. 837-840, 2004.
12. S.-H. Woo et al., "Offset voltage estimation model for latch-type sense amplifiers," Circuits, Devices Systems, IET, vol. 4, no. 6, pp. 503 -513, 2010.
13. E. Alon et al., "Circuits and techniques for high-resolution measurement of on-chip power supply noise," JSSCC, vol. 40, no. 4, pp. 820-828, 2005.
14. S. Naffziger et al., "The implementation of a 2-core, multi-threaded itanium family processor," JSSCC, vol. 41, no. 1, pp. 197-209, 2006. (Pubitemid 43145977)
15. S. Assefa et al., "Cmos-integrated optical receivers for on-chip interconnects,"Selected Topics in Quantum Electronics, IEEE Journal of, vol. 16, no. 5, pp. 1376-1385, sept.-oct. 2010.
16. C. Kromer et al., "A low-power 20-ghz 52-db-ohm transimpedance amplifier in 80-nm CMOS," JSSCC, vol. 39, no. 6, pp. 885-894, 2004.
17. A. Emami-Neyestanak et al., "A 1.6 gb/s, 3 mw cmos receiver for optical communication," VLSI '02, pp. 84-87, 2002.
18. A. Bhatnagar et al., "Receiverless clocking of a cmos digital circuit using short optical pulses," in LEOS '02, vol. 1, 2002, pp. 127-128.
19. F. Tavernier et al., "High-speed optical receivers with integrated photodiode in 130 nm cmos," JSSCC, vol. 44, no. 10, pp. 2856-2867, 2009.
20. A. Strak et al., "Analysis of timing jitter in inverters induced by powersupply noise," in DTIS '06, sept. 2006, pp. 53-56.
21. J. S. Orcutt et al., "Nanophotonic integration in state-of-the-art CMOS foundries," Opt. Express, vol. 19, no. 3, pp. 2335-2346, Jan 2011.
22. S. Selvaraja et al., "Fabrication of uniform photonic devices using 193nm optical lithography in silicon-on-insulator," ECIO '08, 2008.
23. M. S. Nawrocka et al., "Tunable silicon microring resonator with wide free spectral range," Applied Physics Letters, vol. 89, no. 7, p. 071110, 2006.
24. V. Raghunathan et al., "Athermal silicon ring resonators," in Integrated Photonics Research, Silicon and Nanophotonics. Optical Society of America, 2010, p. IMC5.