Light speed arbitration and flow control for nanophotonic interconnects

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 304-315

  Vantrease, Dana ^a   Binkert, Nathan ^b   Schreiber, Robert ^b   Lipasti, Mikko H ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

C.1.2 computer systems organization : multiprocessors; Design; Interconnection architectures; Performance

Indexed keywords

ARBITRATION PROTOCOLS; C.1.2 [COMPUTER SYSTEMS ORGANIZATION]: MULTIPROCESSORS; CHANNEL PROTOCOLS; CHANNEL UTILIZATION; COMPUTER SYSTEMS ORGANIZATION; HIGH BANDWIDTH; INTERCONNECTION ARCHITECTURE; LOW LATENCY; LOW POWER; LOW PRIORITIES; MANY-CORE; NANOPHOTONIC DEVICES; ON CHIPS; ON-CHIP OPTICAL INTERCONNECTS; OPTICAL CHANNELS; OPTICAL INTERCONNECT; PRIORITIZATION; SILICON WAVEGUIDE; SINGLE CYCLE; TIME OF FLIGHT;

COMPUTER ARCHITECTURE; INTEGRATED OPTICS; LIGHT; MULTIPROCESSING SYSTEMS; NANOPHOTONICS; OPTICAL INSTRUMENTS; OPTICAL INTERCONNECTS; OPTICAL PROPERTIES; TELECOMMUNICATION SYSTEMS; WAVEGUIDES;

LIGHT TRANSMISSION;

EID: 76749143733     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669152     Document Type: Conference Paper

References (30)

1. J. Ahn, M. Fiorentino, R. Beausoleil, N. Binkert, A. Davis, D. Fattal, N. Jouppi, M. McLaren, C. Santori, R. Schreiber, et al. Devices and architectures for photonic chip-scale integration. Applied Physics A: Materials Science & Processing, 95(4):989-997, 2009.
2. ANSI/IEEE. Local Area Networks: Token Ring Access Method and Physical Layer Specifications, Std 802.5. Technical report, 1989.
3. C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth, M. Popvic, H. Li, H. Smitth, J. Hoyt, F. Kartner, R. Ram, V. Stojanovic, and K. Asanovic. Building manycore processor-to-DRAM networks with monolithic silicon photonics. In Hot Interconnects, 2008.
4. D. Bertsekas and R. Gallager. Data Networks. Prentice Hall, 1992.
5. N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26(4):52-60, Jul/Aug 2006.
6. K. Bogineni, K. M. Sivalingam, and P. W. Dowd. low-complexity multiple access protocols for wavelength-division multiplexed photonic networks. IEEE Journal on Selected Areas in Communications, 11:590-604, 1993.
7. M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi. Phastlane: a rapid transit optical routing network. In ISCA '09, pages 441-450, New York, NY, USA, 2009. ACM.
8. I. Cidon and Y. Ofek. Metaring-a full-duplex ring with fairness and spatial reuse. IEEE Transactions on Communications, 41(1):110-120, 1993.
9. A. Falcon, P. Faraboschi, and D. Ortega. Combining Simulation and Virtualization through Dynamic Sampling. In ISPASS, Apr 2007.
10. J.-H. Ha and T. M. Pinkston. A new token-based channel access protocol for wavelength division multiplexed multiprocessor interconnects. Journal of Parallel Distributed Computing, 60(2):169-188, 2000.
11. A. Joshi, C. Batten, Y. Kwon, S. Beamer, I. Shamim, K. Asanovic, and V. Stojanovic. Silicon-Photonic Clos Networks for Global On-Chip Communication. In NOCS '09, 2009.
12. M. Karol, M. Hluchyj, and S. Morgan. Input versus output queueing on a space-division packet switch. Communications, IEEE Transactions on, 35(12):1347-1356, 1987.
13. N. Kirman, M. Kirman, R. K. Dokania, J. F. Martinez, A. B. Apsel, M. A. Watkins, and D. H. Albonesi. Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. In MICRO'06, pages 492-503, Washington, DC, USA, 2006. IEEE Computer Society.
14. A. Kodi and A. Louri. Design of a high-speed optical interconnect for scalable shared memory multiprocessors. In High Performance Interconnects, 2004. Proceedings. 12th Annual IEEE Symposium on, pages 92-97, 2004.
15. A. Kodi and A. Louri. Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (hpc) systems. In SC '07: Proceedings of the 2007 ACM/IEEE conference on Supercomputing, pages 1-12, New York, NY, USA, 2007. ACM.
16. P. Krishnamurthy, M. Franklin, and R. Chamberlain. Dynamic reconfiguration of an optical interconnect. In ANSS '03, page 89, Washington, DC, USA, 2003. IEEE Computer Society.
17. M. A. Marsan, A. Bianco, E. Leonardi, A. Morabito, and F. Neri. All-optical WDM multi-rings with difierentiated QoS. IEEE Communications Magazine, 37(2):58-66, 1999.
18. N. McKeown. The iSLIP scheduling algorithm for input-queued switches. IEEE/ACM Trans. Netw., 7(2):188-201, 1999.
19. C. Minkenberg, F. Abel, P. Muller, R. Krishnamurthy, M. Gusat, P. Dill, I. Iliadis, R. Luijten, B. R. Hemenway, R. Grzybowski, and E. Schiattarella. Designing a crossbar scheduler for hpc applications. IEEE Micro, 26(3):58-71, 2006.
20. S. S. Mukherjee, F. Silla, P. Bannon, J. Emer, S. Lang, and D. Webb. A comparative study of arbitration algorithms for the alpha 21364 pipelined router. SIGOPS, 36(5):223-234, 2002.
21. Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A. Choudhary. Firefly: illuminating future network-on-chip with nanophotonics. In ISCA '09, pages 429-440, New York, NY, USA, 2009. ACM.
22. J. Pierce. How far can data loops go? IEEE Transactions on Communications, 20(3):527-530, Jun 1972.
23. C. Qiao and R. G. Melhem. Time-division optical communications in multiprocessor arrays. In SC '91, pages 644-653, New York, NY, USA, 1991. ACM.
24. A. Shacham, B. G. Lee, A. Biberman, K. Bergman, and L. P. Carloni. Photonic NoC for DMA Communications in Chip Multiprocessors. In Proceedings of Hot Interconnects, pages 29-35, Aug 2007.
25. Y. Tamir and G. L. Frazier. high-performance Multi-Queue Buffers for VLSI Communications Switches. SIGARCH Computer Architecture News, 16(2):343-354, 1988.
26. D. Vantrease, R. Schreiber, M. Monchiero, M. McLaren, N. P. Jouppi, M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, and J. H. Ahn. Corona: System Implications of Emerging Nanophotonic Technology. In ISCA-35, pages 153-164, 2008.
27. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA, pages 24-36, Jun 1995.
28. Q. Xu, D. Fattal, and R. Beausoleil. Silicon microring resonators with 1.5-μm radius. Optics Express, 16(6):4309-4315, 2008.
29. Q. Xu, B. Schmidt, S. Pradhan, and M. Lipson. Micrometre-scale silicon electro-optic modulator. Nature, 435:325, May 2005.
30. L. Zhang, M. Song, T. Wu, L. Zou, R. G. Beausoleil, and A. E. Willner. Embedded ring resonators for microphotonic applications. Optics Letters, 33(7):1978-1980, 2008.