Characterizing processor thermal behavior

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2010, Pages 193-204

  Mesa Martínez, Francisco Javier ^a   Ardestani, Ehsan K ^a   Renau, Jose ^a  

^a University of California Santa Cruz   (United States)

Author keywords

Microarchitecture; Temperature; Thermal simulation

Indexed keywords

A-THERMAL; DOMINANT FACTOR; LEAKAGE POWER CONSUMPTION; MATCHINGS; MICRO ARCHITECTURES; MICROARCHITECTURE; MODERN PROCESSORS; REAL PROCESSORS; SIMPOINT; SIMULATION TIME; STATISTICAL SAMPLING; THERMAL BEHAVIORS; THERMAL CHARACTERISTICS; THERMAL CHARACTERIZATION; THERMAL MODELING; THERMAL SIMULATIONS; THERMAL TRANSIENTS;

COMPUTER OPERATING SYSTEMS; LINGUISTICS; NANOTECHNOLOGY; SAMPLING;

COMPUTER SIMULATION;

EID: 77952258085     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1736020.1736043     Document Type: Conference Paper

References (28)

1. R. M. Averill, K. G. Barkley, M. A. Bowen, P. J. Camporese, A. H. Dansky, R. F. Hatch, D. E. Hoffman, M. D. Mayo, S. A. McCabe, T. G. McNamara, T. J. McPherson, G. A. Northrop, L. Sigal, H. H. Smith, D. A. Webber, and P. M. Williams. Chip integration Methodology for the IBM S/390 G5 and G6 Custom Microprocessor. In IBM Jornal of Research and Development, pages 681-706, Sep 1999.
2. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a Framework for Architectural-Level Power Analysis and Optimizations. In Proceedings of the 27th annual International Symposium on Computer Architecture (ISCA), pages 83-94, Jun 2000.
3. A. Coskun, R. Strong, D. Tullsen, and T. Rosing. Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. In Proceeding of the 11th International joint Conference on Measurement and Modeling of Computer Systems (SIGMETRICS), pages 169-180, Jun 2009.
4. B. Curran, E. Fluhr, J. Paredes, L. Sigal, J. Friedrich, Y.-H. Chan, and C. Hwang. Power-constrained high-frequency circuits for the IBM POWER6 microprocessor. IBM J. Res. Dev., 51(6):715-731, 2007.
5. A. Dhodapkar and J. Smith. Comparing Program Phase Detection Techniques. In Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pages 217-228, Dec 2003.
6. H. Hamann, J. Lacey, A.Weger, and J.Wakil. Spatially-resolved imaging of microprocessor power (SIMP): hotspots in microprocessors. In Thermal and Thermomechanical Phenomena in Electronics Systems, pages 121-125, May 2006.
7. S. Heo, K. Barr, and K. Asanović. Reducing power density through activity migration. In Proceedings of the 2003 International Symposium on Low power electronics and design (ISLPED), pages 217-222, Aug 2003.
8. W. Huang, M. Stant, K. Sankaranarayanan, R. Ribando, and K. Skadron. Many-core design from a thermal perspective. In Proceedings of the 45th annual conference on Design Automation (DAC), pages 746-749, Jun 2008.
9. W. Huang, K. Skadron, S. Gurumurthi, R. Ribando, and M. Stan. Differentiating the roles of IR measurement and simulation for power and temperature-aware design. In Proceedings of the 2009 International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 1-10, Apr 2009.
10. C. Isci and M. Martonosi. Phase Characterization for Power: Evaluating Control-Flow-Based and Event-Counter-Based Techniques. In Proceedings of the 12th International Symposium on High-Performance Computer Architecture (HPCA), pages 121-132, Jan 2006.
11. S. Jarp, R. Jurga, and A. Nowak. Perfmon2: a leap forward in performance monitoring. J. Phys.: Conf. Ser., 119:042017, 2008.
12. E. K.Ardestani, F. Mesa-Martínez, and J. Renau. Cooling Solutions for Processor Infrared Thermography. In Proceeding of 26th Annual Thermal Measurement, Modeling and Management Symposium (SEMI-THERM), Feb 2010.
13. B. Lee and T. Kim. Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension. In Proceedings of the 13th Asia and South Pacific Design Automation Conference(ASP-DAC), pages 703-707, Jan 2008.
14. W. Liu, X. Jin, J. Chen, M.-C. Jeng, Z. Liu, Y. Cheng, K. Chen, M. Chan, K. Hui, J. Huang, R. Tu, P. Ko, and C. Hu. BSIM 3v3.2 MOSFET Model Users' Manual. Technical Report UCB/ERL M98/51, EECS Department, University of California, Berkeley, 1998. URL http://www.eecs.berkeley.edu/Pubs/TechRpts/1998/ 3486.html.
15. F. Mesa-Martínez, J. Nayfach-Battilana, and J. Renau. Power model validation through thermal measurements. In Proceedings of the 34th annual International Symposium on Computer architecture (ISCA), pages 302-311, Jun 2007.
16. H. D. Mogal and K. Bazargan. Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. In Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pages 302-305, Nov 2008.
17. R. Mukherjee and S. Memik. Systematic temperature sensor allocation and placement for microprocessors. In Proceedings of the 43rd annual conference on Design automation (DAC), pages 542-547, Jul 2006.
18. R. Mukherjee, S. Mondal, and S. Memik. Thermal sensor allocation and placement for reconfigurable systems. In Proceedings of the 2006 IEEE/ACM International Conference on Computer-aided design (ICCAD), pages 437-442, Nov 2006.
19. N. Nethercote and J. Seward. Valgrind: a framework for heavyweight dynamic binary instrumentation. SIGPLAN Not., 42(6):89-100, Jun 2007.
20. V. Nookala, D. Lilja, and S. Sapatnekar. Temperature-aware floorplanning of microarchitecture blocks with ipc-power dependence modeling and transient analysis. In Proceedings of the 2006 International Symposium on Low Power Electronics and Design (ISLPED), pages 298-303, Oct 2006.
21. A. Phansalkar, A. Joshi, L. Eeckhout, and L. John. Measuring program similarity: Experiments with SPEC CPU benchmark suites. In Proceedings of the 2005 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pages 10-20, Mar 2005.
22. A. Phansalkar, A. Joshi, and L. John. Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. In Proceedings of the 34th annual International Symposium on Computer architecture (ISCA), pages 412-423, Jun 2007.
23. K. Rangan, G.-Y. Wei, and D. Brooks. Thread motion: fine-grained power management for multi-core systems. SIGARCH Comput. Archit. News, 37(3):302-313, 2009.
24. T. Sherwood, E. Perelman, G. Hamerly, and B. Calder. Automatically characterizing large scale program behavior. In Proceedings of the 10th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), volume 30, pages 45-57, Oct 2002.
25. T. Sherwood, S. Sair, and B. Calder. Phase tracking and prediction. In Proceedings of the 30th annual International Symposium on Computer architecture (ISCA), pages 336-349, Jun 2003.
26. K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan. Temperature-Aware Microarchitecture. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pages 2-13, Jun 2003.
27. J. Srinivasan, A. Sarita, P. Bose, and R. Jude. Lifetime reliability: toward an architectural solution. In IEEE MICRO, volume 25, pages 70-80, 2005.
28. Y. Wu and C. Yang. Joint exploration of architectural and physical design spaces with thermal consideration. In Proceedings of the 2005 International Symposium on Low power electronics and design (ISLPED), pages 123-126, Aug 2005.