Improving write operations in MLC phase change memory

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 201-210

  Jiang, Lei ^a   Zhao, Bo ^a   Zhang, Youtao ^b   Yang, Jun ^a   Childers, Bruce R ^b  

^a PA 15260   (United States)

^b UNIVERSITY OF PITTSBURGH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCESS LATENCY; ACCESS TIME; ARCHITECTURAL INNOVATION; CELL PROCESS; COMPOSITION FLUCTUATIONS; ERROR CORRECTION CODES; FABRICATION COST; GROWING DEMAND; HIGH DENSITY; LOW LEAKAGE; MODERN COMPUTER SYSTEMS; MULTILEVEL CELL; MULTIPLE BITS; PERFORMANCE IMPROVEMENTS; PRECISE CONTROL; RESISTANCE LEVEL; SINGLE CELLS; STATE OF THE ART; STORAGE OVERHEAD; WRITE OPERATIONS;

COMPUTER ARCHITECTURE; SUPERCOMPUTERS;

COMPUTER SYSTEMS;

EID: 84860323531     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6169027     Document Type: Conference Paper

References (31)

1. S. Borkar, "Thousands Core Chips - a Technology Perspective," in DAC, 2007.
2. C. Lefurgy et al., "Energy Management for Commercial Servers," in IEEE Computer, 2003.
3. The ITRS Report, 2009. http://www.itrs.net/
4. F. Bedeschi et al., "A Bipolar-selected Phase Change Memory Featuring Multi-level Cell Storage," in JSSC, 2009.
5. S. Raoux et al., "Phase-Change Random Access Memory: a scalable technology," in IBM J. Res. Dev., 2008.
6. M.K. Qureshi et al., "Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing," in HPCA, 2010.
7. M.K. Qureshi et al., "Morphable Memory System: a Robust Architecture for Exploiting Multi-level Phase Change Memories," in ISCA, 2010.
8. G. Sun et al., "A frequent-value based PRAM memory architecture,"in ASP-DAC, 2011.
9. A. Cabrini et al., "Voltage-driven Multilevel Programming in Phase Change Memories," in IEEE MTDT, 2009.
10. A.R. Alameldeen and D.A.Wood, "Adaptive Cache Compression for High-Performance Processors," in ISCA, 2004.
11. D. Mantegazza et al., "Statistical Analysis and Modeling of Programming and Retention in PCM Arrays," in IEDM, 2007.
12. M. Boniardi et al., "Impact of Material Composition on the Write Performance of Phase-Change Memory Device," in Intl. Memory Workshop, 2010.
13. W. Zhang and T. Li, "Characterizing and Mitigating the Impact of Process Variations on Phase Change based Memory Systems," in MICRO, 2009.
14. L. Jiang et al., "Enhancing Phase Change Memory Lifetime through Fine-Grained Current Regulation and Voltage Upscaling," in ISLPED, 2011.
15. T. Nirschl et al., "Write Strategies for 2 and 4-bit Multi-level Phase-Change Memory," in IEDM, 2007.
16. A. Pantazi et al., "Multilevel PCM Modeling and Experimental Characterization,"in E-PCOS, 2009.
17. M. Joshi et al., "Mercury: A Fast and Energy-Efficient Multi-level Cell based Phase Change Memory System," in HPCA, 2011.
18. P. Zhou et al., "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," in ISCA, 2009.
19. A.C. Calligaro et al., "Comparative Analysis of Sensing Schemes for Multilevel Non-volatile Memories," in ICISS, 1997.
20. S. Schechter et al., "Use ECP, not ECC, for Hard Failures in Resistive Memories," in ISCA, 2010.
21. M. K. Qureshi et al., "Enhancing Lifetime and Security of PCM-based Main Memory with Start-Gap Wear Leveling," in MICRO, 2009.
22. K. Fang et al., "Memory Architecture for Integrating Emerging Memory Technologies," in PACT, 2011.
23. K. Kim and S. Ahn, "Reliability Investigations for Manufacturable High Density PRAM," in IRPS, 2005.
24. HPCS Scalable Synthetic Compact Applications #2 Graph Analysis. http://www.graphanalysis.org/benchmark/
25. STREAM. http://www.cs.virginia.edu/stream/
26. D.M. Tullsen and J.A. Brown, "Handling Long-latency Loads in a Simultaneous Multithreading Processor," in MICRO, 2001.
27. J. Warnock et al., "A 5.2Ghz Microprocessor Chip for the IBM zEnterprise System," in ISSCC, 2011.
28. Doe Hyun Yoon et al., "FREE-p: Protecting non-volatile memory against both hard and soft errors", in HPCA, 2011.
29. R. Naseer, and J. Draper, "DEC ECC design to improve memory reliability in Sub-100nm technologies," in ICECS, 2008.
30. J. Thatcher et al., "Nand flash solid state storage for the enterprise: An in-depth look at reliability," in SNIA, 2009.
31. M.K. Qureshi et al., "Scalable High Performance Main Memory System using Phase-Change Memory Technology," in ISCA, 2009.