Characterizing and mitigating the impact of process variations on phase change based memory systems

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2009, Pages 2-13

  Zhang, Wangyuan ^a   Li, Tao ^a  

^a University of Florida   (United States)

Author keywords

Memory system; Phase change memory; Process variation

Indexed keywords

CMOS PROCESSING TECHNOLOGY; COMBINATIONAL LOGIC; CONVENTIONAL TRANSISTORS; CROSS-LAYER APPROACH; DESIGN PARAMETERS; DESIGN SOLUTIONS; DESIGN TECHNIQUE; DYNAMIC RANDOM ACCESS MEMORY; ENDURANCE IMPROVEMENT; INTEGRATION DENSITY; MAIN MEMORY; MANUFACTURING STAGES; MEMORY SYSTEM; MEMORY SYSTEMS; NANO SCALE; NANO-SCALE FABRICATION; NON-VOLATILE MEMORIES; NON-VOLATILE MEMORY DESIGN; PHASE CHANGE; PHASE-CHANGE RANDOM ACCESS MEMORY; PHASE-CHANGE-BASED MEMORIES; POWER BUDGETS; POWER EFFICIENCY; POWER SAVINGS; PROCESS VARIATION; PROCESSING TECHNOLOGIES; SCALING DOWN; SMALL FEATURES; STORAGE CELLS; SYSTEM-LEVEL SUPPORT; VLSI TECHNOLOGY;

DESIGN; DURABILITY; DYNAMIC RANDOM ACCESS STORAGE; NANOSTRUCTURED MATERIALS; TECHNOLOGY;

PHASE CHANGE MEMORY;

EID: 76749137639     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1669112.1669116     Document Type: Conference Paper

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