-
2
-
-
70450235471
-
Architecting Phase Change Memory As a Scalable DRAM Alternative
-
B. Lee, E. Ipek, O. Mutlu, and D. Burger, Architecting Phase Change Memory As a Scalable DRAM Alternative, ISCA 2009.
-
ISCA 2009
-
-
Lee, B.1
Ipek, E.2
Mutlu, O.3
Burger, D.4
-
3
-
-
58149231291
-
A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage
-
F. Bedeschi, R. Fackenthal, C. Resta, E. Donze, M. Jagasivamani, E. Buda, F. Pellizzer, D. Chow, A. Cabrini, G. Calvi, R. Faravelli, A. Fantini, G. Torelli, D. Mills, R. Gastaldi, and G. Casagrande, A Bipolar-Selected Phase Change Memory Featuring Multi-Level Cell Storage, JSSC 2009.
-
JSSC 2009
-
-
Bedeschi, F.1
Fackenthal, R.2
Resta, C.3
Donze, E.4
Jagasivamani, M.5
Buda, E.6
Pellizzer, F.7
Chow, D.8
Cabrini, A.9
Calvi, G.10
Faravelli, R.11
Fantini, A.12
Torelli, G.13
Mills, D.14
Gastaldi, R.15
Casagrande, G.16
-
4
-
-
42149105894
-
Write Strategies for 2 and 4-bit Multi-Level Phase- Change Memory
-
T. Nirschl, J. Phipp, T. Happ, G. Burr, B. Rajendran, M. Lee, A. Schrott, M. Yang, M. Breitwisch, C. Chen, E. Joseph, M. Lamorey, R.Cheek, S. Chen, S. Zaidi, S. Raoux, Y. Chen, Y. Zhu, R. Bergmann, H. Lung, and C. Lam, Write Strategies for 2 and 4-bit Multi-Level Phase- Change Memory, IEDM 2007.
-
IEDM 2007
-
-
Nirschl, T.1
Phipp, J.2
Happ, T.3
Burr, G.4
Rajendran, B.5
Lee, M.6
Schrott, A.7
Yang, M.8
Breitwisch, M.9
Chen, C.10
Joseph, E.11
Lamorey, M.12
Cheek, R.13
Chen, S.14
Zaidi, S.15
Raoux, S.16
Chen, Y.17
Zhu, Y.18
Bergmann, R.19
Lung, H.20
Lam, C.21
more..
-
5
-
-
4544337857
-
An 8Mb Demonstrator for High-Density 1.8V Phase-Change Memories
-
F. Bedeschi, C. Resta, O. Khouri, E. Buda, L. Costa, M. Ferraro, F. Pellizzer, F. Ottogalli, A. Pirovano, M. Tosi, R. Bez, R. Gastaldi and G. Casagrande, An 8Mb Demonstrator for High-Density 1.8V Phase-Change Memories, VLSI Symp. Tech.Dig. 2004.
-
VLSI Symp. Tech.Dig. 2004
-
-
Bedeschi, F.1
Resta, C.2
Khouri, O.3
Buda, E.4
Costa, L.5
Ferraro, M.6
Pellizzer, F.7
Ottogalli, F.8
Pirovano, A.9
Tosi, M.10
Bez, R.11
Gastaldi, R.12
Casagrande, G.13
-
6
-
-
67649099945
-
SET and RESET Pulse Characterization in BJT-Selected Phase Change Memories
-
F. Bedeschi, E. Bonizzoni, G. Casagrande, R. Gastaldi, C. Resta, G. Torelli, and D. ZelLa, SET and RESET Pulse Characterization in BJT-Selected Phase Change Memories, ISCAS 2005.
-
ISCAS 2005
-
-
Bedeschi, F.1
Bonizzoni, E.2
Casagrande, G.3
Gastaldi, R.4
Resta, C.5
Torelli, G.6
ZelLa, D.7
-
7
-
-
46649093142
-
A Compact Model of Phase-Change Memory Based on Rate Equations of Crystallization and Amorphization
-
K. Sonoda, A. Sakai, M. Moniwa, K. Ishikawa,O. Tsuchiya, and Y. Inoue, A Compact Model of Phase-Change Memory Based on Rate Equations of Crystallization and Amorphization, TED 2008.
-
TED 2008
-
-
Sonoda, K.1
Sakai, A.2
Moniwa, M.3
Tsuchiya, K.4
Ishikawa, O.5
Inoue, Y.6
-
8
-
-
37549012274
-
Novel One-Mask Self-Heating Pillar Phase Change Memory
-
T. Happ, M. Breitwitsch, A. Schrott , J. Philipp, M. Lee, R. Cheek, T. Nirschl, M. Lamorey, C. Ho, S. Chen, C. Chen, E. Joseph, S. Zaidi, G. Burr, B. Yee, Y. Chen, S Raoux, H. Lung, R. Burgmann, and C. Lam, Novel One-Mask Self-Heating Pillar Phase Change Memory, VLSI Symp. Tech. Dig. 2006.
-
VLSI Symp. Tech. Dig. 2006
-
-
Happ, T.1
Breitwitsch, M.2
Schrott, A.3
Philipp, J.4
Lee, M.5
Cheek, R.6
Nirschl, T.7
Lamorey, M.8
Ho, C.9
Chen, S.10
Chen, C.11
Joseph, E.12
Zaidi, S.13
Burr, G.14
Yee, B.15
Chen, Y.16
Raoux, S.17
Lung, H.18
Burgmann, R.19
Lam, C.20
more..
-
9
-
-
76749137639
-
Characterizing and Mitigating the Impact of Process Variations on Phase Change based Memory Systems
-
W. Zhang and T. Li, Characterizing and Mitigating the Impact of Process Variations on Phase Change based Memory Systems, MICRO 2009.
-
MICRO 2009
-
-
Zhang, W.1
Li, T.2
-
11
-
-
50249177041
-
Physical Interpretation, Modeling and Impact of Phase Change Memory (PCM) Reliability of Resistance Drift due to Chalcogenide Structural Relaxation
-
D. Ielmini, S. Lavizarri, D. Sharma, and A. Lacaita, Physical Interpretation, Modeling and Impact of Phase Change Memory (PCM) Reliability of Resistance Drift due to Chalcogenide Structural Relaxation, IEDM 2007.
-
IEDM 2007
-
-
Ielmini, D.1
Lavizarri, S.2
Sharma, D.3
Lacaita, A.4
-
12
-
-
77952570744
-
Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing
-
M. Qureshi, M. Franceschini, and L. Lastras, Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing, HPCA 2010.
-
HPCA 2010
-
-
Qureshi, M.1
Franceschini, M.2
Lastras, L.3
-
13
-
-
70450277571
-
A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology
-
P. Zhou, B. Zhao, J. Yang and Y. Zhang, A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology, ISCA 2009.
-
ISCA 2009
-
-
Zhou, P.1
Zhao, B.2
Yang, J.3
Zhang, Y.4
-
15
-
-
77956570937
-
Improving Privacy and Lifetime of PCM Based Main Memory
-
J. Kong and H. Zhou, Improving Privacy and Lifetime of PCM Based Main Memory, DSN 2010.
-
DSN 2010
-
-
Kong, J.1
Zhou, H.2
-
16
-
-
38949186007
-
VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects
-
S. Sarangi, B. Greskamp, R. Teodorescu, J. Nakano, A Tiwari, and J. Torrellas, VARIUS: A Model of Process Variation and Resulting Timing Errors for Microarchitects, TSM 2008.
-
TSM 2008
-
-
Sarangi, S.1
Greskamp, B.2
Teodorescu, R.3
Nakano, J.4
Tiwari, A.5
Torrellas, J.6
-
17
-
-
36949014308
-
PTLSim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator
-
M. Yourst, PTLSim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator, ISPASS 2007.
-
ISPASS 2007
-
-
Yourst, M.1
-
18
-
-
79955902629
-
DRAMSim: A Memory System Simulator
-
D. Wang, B. Ganesh, N. Tuaychareon, K. Baynes, A. Jaleel and B. Jacob, DRAMSim: A Memory System Simulator, SIGARCH 2005.
-
SIGARCH 2005
-
-
Wang, D.1
Ganesh, B.2
Tuaychareon, N.3
Baynes, K.4
Jaleel, A.5
Jacob, B.6
-
19
-
-
70450273507
-
Scalable High-Performance Main Memory System Using Phase-Change Memory Technology
-
M. Qureshi, V. Srinivasan, and J.Rivers, Scalable High-Performance Main Memory System Using Phase-Change Memory Technology, ISCA 2009.
-
ISCA 2009
-
-
Qureshi, M.1
Srinivasan, V.2
Rivers, J.3
-
20
-
-
77954972235
-
Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memories
-
M. Qureshi, M. Franceschini, L. Lastras, and J. Karidis, Morphable Memory System: A Robust Architecture for Exploiting Multi-Level Phase Change Memories, ISCA 2010.
-
ISCA 2010
-
-
Qureshi, M.1
Franceschini, M.2
Lastras, L.3
Karidis, J.4
-
21
-
-
33947679297
-
HSPICE Macromodel of PCRAM for Binary and Multilevel Storage
-
X. Wei, L. Shi, R. Walia, T. Chong, R. Zhao, X. Miao, and B. Quek, HSPICE Macromodel of PCRAM for Binary and Multilevel Storage, TED 2006 .
-
TED 2006
-
-
Wei, X.1
Shi, L.2
Walia, R.3
Chong, T.4
Zhao, R.5
Miao, X.6
Quek, B.7
-
23
-
-
0141745746
-
One-Dimensional Heat Conduction Model for an Electrical Phase Change Random Access Memory Device with an 8F2 Memory Cell (F=0.15 μm)
-
D. Kang, D. Ahn, K. Kim, J. Webb, and K. Yi, One-Dimensional Heat Conduction Model for an Electrical Phase Change Random Access Memory Device with an 8F2 Memory Cell (F=0.15 μm), JAP 2003.
-
JAP 2003
-
-
Kang, D.1
Ahn, D.2
Kim, K.3
Webb, J.4
Yi, K.5
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