DEC ECC design to improve memory reliability in sub-100nm technologies

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 586-589

  Naseer, Riaz ^a   Draper, Jeff ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC TECHNOLOGIES; BCH CODES; BLOCK SIZES; CODE DESIGNS; COMPARATIVE ANALYSIS; DECODING LATENCIES; ERROR CORRECTING CODES; IMPLEMENTATION APPROACHES; ITERATIVE DECODING ALGORITHMS; MEMORY RELIABILITIES; PARALLEL DECODING; PROCESS VARIATIONS; RELIABILITY GAINS; SINGLE CYCLES; SOFT ERRORS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DATA STORAGE EQUIPMENT; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; ERROR CORRECTION; MICROPROCESSOR CHIPS; NANOTECHNOLOGY; RELIABILITY; RELIABILITY ANALYSIS; STATIC RANDOM ACCESS STORAGE;

ITERATIVE DECODING;

EID: 57849169110     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674921     Document Type: Conference Paper

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