Voltage-driven multilevel programming in phase change memories

Proceedings of the 2009 IEEE International Workshop on Memory Technology, Design, and Testing, MTDT 2009

Volumn , Issue , 2009, Pages 3-6

  Cabrini, A ^a   Braga, S ^a   Manetto, A ^a   Torelli, G ^a  

^a UNIVERSITY OF PAVIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED VOLTAGES; ELECTRICAL RESISTANCES; IN-PHASE; MEMORY ARRAY; MULTI-LEVEL; MULTILEVEL PROGRAMMING; MULTIPULSES; PROGRAMMING ALGORITHMS; SINGLE CELLS; SINGLE-PULSE; TIME LENGTH;

IMPACT RESISTANCE;

PHASE CHANGE MEMORY;

EID: 72349096382     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MTDT.2009.11     Document Type: Conference Paper

References (12)

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