100MHz, 0.4W RISC processor with 200MHz multiply-adder, using pulse-register technique

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 39, Issue , 1996, Pages 140-141

  Kozu, Shinichi ^a   Daito, Masayuki ^a   Sugiyama, Yukinori ^a   Suzuki, Hiroaki ^a   Morita, Hiroshi ^a   Nomura, Masahiro ^a   Nadehara, Kouhei ^a   Ishibuchi, Souichiro ^a   Tokuda, Masako ^a   Inoue, Yoshihisa ^a   Nakayama, Takashi ^a   Harigai, Hisao ^a   Yano, Yoichi ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; BUFFER CIRCUITS; BUFFER STORAGE; CARRY LOGIC; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; COUNTING CIRCUITS; PHASE LOCKED LOOPS; REDUCED INSTRUCTION SET COMPUTING; SHIFT REGISTERS; TRANSISTORS;

CHIP PARAMETERS; CONTROL LOGIC; DATAPATH; MULTIPLY ADDER; PULSE REGISTER;

MICROPROCESSOR CHIPS;

EID: 0030087136     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)