-
2
-
-
0030083355
-
Flow-through latch and edge-triggered flip-flop hybrid elements
-
Feb
-
H. Partovi et al., "Flow-through latch and edge-triggered flip-flop hybrid elements," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 138-139.
-
(1996)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 138-139
-
-
Partovi, H.1
-
3
-
-
0030087136
-
A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique
-
Feb
-
S. Kozu et al., "A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 140-141.
-
(1996)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 140-141
-
-
Kozu, S.1
-
4
-
-
0342452492
-
An out-of-order three-way superscalar multimedia floating-point unit
-
Feb
-
A. Scherer et al., "An out-of-order three-way superscalar multimedia floating-point unit," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1999, pp. 94-95.
-
(1999)
Proc. IEEE Int. Solid-State Circuits Conf
, pp. 94-95
-
-
Scherer, A.1
-
5
-
-
0035507074
-
An embedded 32-b microprocessor core for low-power and high-performance applications
-
Nov
-
L. Clark et al., "An embedded 32-b microprocessor core for low-power and high-performance applications," IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1599-1608, Nov. 2001.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1599-1608
-
-
Clark, L.1
-
6
-
-
0035505541
-
A multigigahertz clocking scheme for the Pentium 4 microprocessor
-
Nov
-
N. Kurd et al., "A multigigahertz clocking scheme for the Pentium 4 microprocessor," IEEE Journal of Solid-State Circuits, vol. 36, no. 11, pp. 1647-1653, Nov. 2001.
-
(2001)
IEEE Journal of Solid-State Circuits
, vol.36
, Issue.11
, pp. 1647-1653
-
-
Kurd, N.1
-
7
-
-
0036858569
-
The implementation of the Itanium 2 microprocessor
-
Nov
-
S. Naffziger et al., "The implementation of the Itanium 2 microprocessor," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1448-1460, Nov. 2002.
-
(2002)
IEEE Journal of Solid-State Circuits
, vol.37
, Issue.11
, pp. 1448-1460
-
-
Naffziger, S.1
-
8
-
-
10744221866
-
A 1.3-GHz fifth-generation SPARC64 microprocessor
-
Nov
-
H. Ando et al., "A 1.3-GHz fifth-generation SPARC64 microprocessor," IEEE Journal of Solid-State Circuits, vol. 38, no. 11, pp. 1896-1905, Nov. 2003.
-
(2003)
IEEE Journal of Solid-State Circuits
, vol.38
, Issue.11
, pp. 1896-1905
-
-
Ando, H.1
-
9
-
-
0025464163
-
Clock skew optimization
-
July
-
J. Fishburn, "Clock skew optimization," IEEE Trans. on Computers, vol. 39, no. 7, pp. 945-951, July 1990.
-
(1990)
IEEE Trans. on Computers
, vol.39
, Issue.7
, pp. 945-951
-
-
Fishburn, J.1
-
10
-
-
0346868084
-
Chip clocking effect on performance for IBM's SA-27E ASIC technology
-
K. Carrig, "Chip clocking effect on performance for IBM's SA-27E ASIC technology," IBM Micronews, vol. 6, no. 3, pp. 12-16, 2000.
-
(2000)
IBM Micronews
, vol.6
, Issue.3
, pp. 12-16
-
-
Carrig, K.1
-
11
-
-
0348040124
-
Clock scheduling and clocktree construction for high performance ASICs
-
Nov
-
S. Held et al., "Clock scheduling and clocktree construction for high performance ASICs," in Proc. Int. Conf. on Computer-Aided Design, Nov. 2003, pp. 232-239.
-
(2003)
Proc. Int. Conf. on Computer-Aided Design
, pp. 232-239
-
-
Held, S.1
-
12
-
-
57849154404
-
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits
-
Nov
-
H. Lee, S. Paik, and Y. Shin, "Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits," in Proc. Int. Conf. on Computer-Aided Design, Nov. 2008, pp. 224-229.
-
(2008)
Proc. Int. Conf. on Computer-Aided Design
, pp. 224-229
-
-
Lee, H.1
Paik, S.2
Shin, Y.3
-
14
-
-
0020504458
-
Optimizing synchronous circuitry by retiming
-
Mar
-
C. Leiserson, F. Rose, and J. Saxe, "Optimizing synchronous circuitry by retiming," in Proc. CalTech Conf. on VLSI, Mar. 1983, pp. 23-36.
-
(1983)
Proc. CalTech Conf. on VLSI
, pp. 23-36
-
-
Leiserson, C.1
Rose, F.2
Saxe, J.3
-
15
-
-
0030260869
-
Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits
-
Oct
-
S. Sapatnekar and R. Deokar, "Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits," IEEE Trans. on Computer-Aided Design, vol. 15, no. 10, pp. 1237-1248, Oct. 1996.
-
(1996)
IEEE Trans. on Computer-Aided Design
, vol.15
, Issue.10
, pp. 1237-1248
-
-
Sapatnekar, S.1
Deokar, R.2
-
16
-
-
20344385187
-
-
Kluwer Academic Publishers
-
S. Sapatnekar, Timing, Kluwer Academic Publishers, 2004.
-
(2004)
Timing
-
-
Sapatnekar, S.1
-
17
-
-
33746763910
-
Retiming synchronous circuitry
-
June
-
C. Leiserson and J. Saxe, "Retiming synchronous circuitry," Algorithmica, vol. 6, no. 1-6, pp. 5-35, June 1991.
-
(1991)
Algorithmica
, vol.6
, Issue.1-6
, pp. 5-35
-
-
Leiserson, C.1
Saxe, J.2
-
19
-
-
13444306519
-
Clock period minimization method of semi-synchronous circuits by delay insertion
-
Dec
-
Y. Kohira and A. Takahashi, "Clock period minimization method of semi-synchronous circuits by delay insertion," in Proc. Asia-Pacific Conf. on Circuits and Systems, Dec. 2004, pp. 533-536.
-
(2004)
Proc. Asia-Pacific Conf. on Circuits and Systems
, pp. 533-536
-
-
Kohira, Y.1
Takahashi, A.2
-
20
-
-
46649093796
-
Clock skew scheduling with delay padding for prescribed skew domains
-
Jan
-
C. Lin and H. Zhou, "Clock skew scheduling with delay padding for prescribed skew domains," in Proc. Asia South Pacific Design Automation Conf., Jan. 2007, pp. 541-546.
-
(2007)
Proc. Asia South Pacific Design Automation Conf
, pp. 541-546
-
-
Lin, C.1
Zhou, H.2
-
21
-
-
0027797124
-
Minimum padding to satisfy short path constraints
-
Nov
-
N. Shenoy, R. Brayton, and A. Sangiovanni-Vincentelli, "Minimum padding to satisfy short path constraints," in Proc. Int. Conf. on Computer-Aided Design, Nov. 1993, pp. 156-161.
-
(1993)
Proc. Int. Conf. on Computer-Aided Design
, pp. 156-161
-
-
Shenoy, N.1
Brayton, R.2
Sangiovanni-Vincentelli, A.3
-
22
-
-
76349091843
-
-
http://www.opencores.org/.
-
-
-
|