Pulsed-latch circuits to push the envelope of ASIC design

2010 International SoC Design Conference, ISOCC 2010

Volumn , Issue , 2010, Pages 150-153

  Paik, Seungwhun ^a   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; LATCH CIRCUITS; LOWER-POWER CONSUMPTION; POTENTIAL SOLUTIONS; QUANTITATIVE RESULT; TIMING MODELS;

DESIGN; ELECTRIC POWER SUPPLIES TO APPARATUS; INTEGRATED CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 79851484870     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SOCDC.2010.5682949     Document Type: Conference Paper

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