A robust, fast pulsed flip-flop design

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2008, Pages 119-122

  Venkatraman, Arunprasad ^a   Garg, Rajesh ^a   Khatri, Sunil P ^a  

^a TEXAS A AND M UNIVERSITY   (United States)

Author keywords

Flip flop; Latch

Indexed keywords

AREA EFFICIENT; FLIP-FLOP; GENERATOR CIRCUITS; LATCH; LAYOUT AREAS; LOW POWERS; MASTER SLAVES; MONTE CARLO SIMULATIONS; VLSI DESIGNS;

DESIGN; LAKES; MONTE CARLO METHODS; PULSE CIRCUITS; PULSE GENERATORS; SIGNAL GENERATORS;

FLIP FLOP CIRCUITS;

EID: 56849083623     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1366110.1366140     Document Type: Conference Paper

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