Statistical time borrowing for pulsed-latch circuit designs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 675-680

  Paik, Seungwhun ^a   Yu, Lee Eun ^a   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALLOCATION ALGORITHM; CLOCK PERIOD; COMBINATIONAL BLOCKS; LATCH CIRCUITS; LATCH PAIR; PULSE WIDTH; SHORT PULSE; STATISTICAL APPROACH; TIME BORROWING; TIMING ANALYSIS; TIMING YIELD; WORST CASE;

CLOCKS; COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; RANDOM PROCESSES; RANDOM VARIABLES; TIME MEASUREMENT;

FLIP FLOP CIRCUITS;

EID: 77951210930     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419801     Document Type: Conference Paper

References (12)

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