Pulsed-latch-based clock tree migration for dynamic power reduction

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2011, Pages 39-44

  Lin, Hong Ting ^a   Chuang, Yi Lin ^b   Ho, Tsung Yi ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

^b NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Clock Network Synthesis; Power Reduction; Pulsed Latch

Indexed keywords

CIRCUIT DESIGNS; CLOCK NETWORK SYNTHESIS; CLOCK TREE; CLOCK TREE SYNTHESIS; DYNAMIC POWER REDUCTION; LOAD BALANCE; POWER REDUCTIONS; POWER SAVINGS; POWER-AWARE; PULSED LATCH; SYNTHESIS ALGORITHMS;

ALGORITHMS; DESIGN; ELECTRIC CLOCKS; FLIP FLOP CIRCUITS; LOW POWER ELECTRONICS; PLANT EXTRACTS; POWER ELECTRONICS;

TREES (MATHEMATICS);

EID: 80052743086     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISLPED.2011.5993601     Document Type: Conference Paper

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