Pulser gating: A clock gating of pulsed-latch circuits

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2011, Pages 190-195

  Kim, Sangmin ^a   Han, Inhak ^a   Paik, Seungwhun ^a   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ASIC DESIGN; CLOCK GATING; LATCH CIRCUITS; LITERAL COUNT; LOW POWER; NETLIST; POWER SAVINGS; TIMING MODELS;

COMPUTER AIDED DESIGN; HEURISTIC ALGORITHMS; INTEGRATED CIRCUITS; PROBABILISTIC LOGICS; PULSE GENERATORS; SIGNAL GENERATORS;

FLIP FLOP CIRCUITS;

EID: 79952961422     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2011.5722182     Document Type: Conference Paper

References (14)

1. S. Kozu et al., "A 100 MHz 0.4W RISC processor with 200 MHz multiply-adder, using pulse-register technique," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 1996, pp. 140-141.
2. S. Naffziger et al., "The implementation of the Itanium 2 microprocessor," IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1448-1460, Nov. 2002.
3. Y. Chuang, S. Kim, Y. Shin, and Y. Chang, "Pulsed-latch aware placement for timing-integrity optimization," in Proc. Design Automation Conf., June 2010, pp. 280-285.
4. S. Shibatani and A. Li, "Pulse-latch approach reduces dynamic power," July 2006, EE Times.
5. L. Benini and G. De Micheli, "Automatic synthesis of low-power gated-clock finite-state machines," IEEE Trans. on Computer-Aided Design, vol. 15, no. 6, pp. 630-643, June 1996.
6. E. Arbel, C. Eisner, and O. Rokhlenko, "Resurrecting infeasible clock-gating functions," in Proc. Design Automation Conf., July 2009, pp. 160-165.
7. S. Ercolani, M. Favalli, M. Damiani, P. Olivo, and B. Riccó, "Estimate of signal probability in combinational logic networks," in Proc. European Test Conf., Apr. 1989, pp. 132-138.
8. C. Tsui, J. Monteiro, M. Pedram, S. Devadas, A. M. Despain, and B. Lin, "Power estimation methods for sequential logic circuits,," IEEE Trans. on VLSI Systems, vol. 3, no. 3, pp. 404-416, Sept. 1995.
9. R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang, "MIS: A multiple-level logic optimization system," IEEE Trans. on Computer-Aided Design, vol. 6, no. 6, pp. 1062-1081, Nov. 1987.
10. OpenCores. [Online]. Available: http://www.opencores.org/
11. Synopsys, "Design Compiler User Guide," Sept. 2008.
12. -, "IC Compiler User Guide," Dec. 2008.
13. E. Sentovich et al., "SIS: a system for sequential circuit synthesis," May 1992, Tech. Rep. UCB/ERL M92/41.
14. Synopsys, "NanoSim User Guide," Sept. 2008.