An effective gated clock tree design based on activity and register aware placement

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 12, 2010, Pages 1639-1648

  Shen, Weixiang ^a   Cai, Yici ^a   Hong, Xianlong ^a   Hu, Jiang ^b  

^a TSINGHUA UNIVERSITY   (China)

^b Department of Electrical and Computer Engineering   (United States)

Author keywords

Activity; gated clock tree; low power; register placement

Indexed keywords

ACTIVITY; CLOCK GATING; CLOCK TREE; CLOCK TREE SYNTHESIS; GATED CLOCKS; INCREMENTAL PLACEMENT; LOW POWER; PHYSICAL INFORMATION; REGISTER PLACEMENT; REGISTER TRANSFER LEVEL; WIRE LENGTH;

DESIGN; ELECTRIC CLOCKS; MICROPROCESSOR CHIPS;

TREES (MATHEMATICS);

EID: 78649499437     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2030156     Document Type: Article

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