Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 224-229

  Hyein, Lee ^a   Seungwhun, Paik ^a   Youngsoo, Shin ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCKS; COMPUTER AIDED DESIGN; DESIGN; ELECTRIC CLOCKS; LOGIC CIRCUITS; SCHEDULING; SEQUENTIAL CIRCUITS; TIMING CIRCUITS; TIMING DEVICES;

ALLOCATION ALGORITHMS; BENCHMARK CIRCUITS; CLOCK PERIODS; CLOCK PULSES; CLOCK SKEW SCHEDULING; CLOCK SKEWS; DESIGN FLOWS; DESIGN PARAMETERS; DISCRETE NUMBERS; GLOBAL CLOCKS; PLACEMENT AND ROUTING; PROCESS VARIATIONS; PULSE WIDTHS; SINGLE PULSES; SYNTHESIS OF; TIMING VERIFICATIONS; UPPER BOUNDS;

FLIP FLOP CIRCUITS;

EID: 57849154404     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681578     Document Type: Conference Paper

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