On the switching parameter variation of metal oxide RRAM - Part II: Model corroboration and device design strategy

IEEE Transactions on Electron Devices

Volumn 59, Issue 4, 2012, Pages 1183-1188

  Yu, Shimeng ^a   Guan, Ximeng ^a   Wong, H S Philip ^a  

^a Stanford University   (United States)

Author keywords

Parameter fluctuation; resistive random access memory (RRAM); resistive switching; switching uniformity; tail bit; variability

Indexed keywords

BI-LAYER; CURRENT FLUCTUATIONS; DEVICE DESIGN; EXPERIMENTAL DATA; GENERATION PROCESS; HIGH-RESISTANCE STATE; METAL OXIDES; OXIDE STRUCTURES; PARAMETER FLUCTUATIONS; RESISTANCE DISTRIBUTION; RESISTANCE STATE; RESISTIVE RANDOM ACCESS MEMORY; RESISTIVE RANDOM ACCESS MEMORY (RRAM); RESISTIVE SWITCHING; STOCHASTIC NATURE; SWITCHING PARAMETERS; TRANSIENT CHARACTERISTIC; TUNNELING GAP; VARIABILITY;

METALLIC COMPOUNDS; RANDOM ACCESS STORAGE; TRANSIENTS;

COMPUTER SIMULATION;

EID: 84859216579     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2012.2184544     Document Type: Article

References (30)

1. R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox-based resistive switching memories-Nanoionic mechanisms, prospects, and challenges," Adv. Mater., vol. 21, no. 25/26, pp. 2632-2663, Jul. 2009.
2. H. Akinaga and H. Shima, "Resistive random access memory (ReRAM) based on metal oxides," Proc. IEEE, vol. 98, no. 12, pp. 2237-2251, Dec. 2010.
3. S. Yu, B. Lee, and H.-S. P. Wong, "Metal oxide resistive switching memory," in Functional Metal Oxide Nanostructures, J. Q. Wu, Ed. Berlin, Germany: Springer-Verlag, 2011.
4. I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S. O. Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and I. T. Moon, "Highly scalable nonvolatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses," in IEDM Tech. Dig., 2004, pp. 587-590.
5. W. C. Chien, Y. R. Chen, Y. C. Chen, A. T. H. Chuang, F. M. Lee, Y. Y. Lin, E. K. Lai, Y. H. Shih, K. Y. Hsieh, and C.-Y. Lu, "A formingfree WOx resistive memory using a novel self-aligned field enhancement feature with excellent reliability and scalability," in IEDM Tech. Dig., 2010, pp. 19.2.1-19.2.4.
6. x based resistive memory with sub-ns switching speed and high endurance," in IEDM Tech. Dig., 2010, pp. 19.7.1-19.7.4.
7. x RRAM device with excellent switching uniformity and reliability for high-density cross-point memory applications," in IEDM Tech. Dig., 2010, pp. 19.5.1-19.5.4.
8. Z.Wei, Y. Kanzawa, K. Arita, Y. Katoh, K. Kawai, S. Muraoka, S.Mitani, S. Fujii, K. Katayama, M. Iijima, T. Mikawa, T. Ninomiya, R. Miyanaga, Y. Kawashima, K. Tsuji, A. Himeno, T. Okada, R. Azuma, K. Shimakawa, H. Sugaya, T. Takagi, R. Yasuhara, K. Horiba, H. Kumigashira, and M. Oshima, "Highly reliable TaOx ReRAM and direct evidence of redox reaction mechanism," in IEDM Tech. Dig., 2008, pp. 1-4.
9. M.-J. Lee, C. B. Lee, D. Lee, S. R. Lee, M. Chang, J. H. Hur, Y.-B. Kim, C.-J. Kim, D. H. Seo, S. Seo, U.-I. Chung, I.-K. Yoo, and K. Kim, "A fast, high-endurance and scalable non-volatile memory device made from asymmetric Ta2O5-x/TaO2-x bilayer structures," Nat. Mater., vol. 10, no. 8, pp. 625-630, Jul. 2011.
10. x RRAM with sub-μA programming current," in Proc. Symp. VLSI Technol., 2011, pp. 22-23.
11. S.-S. Sheu, M.-F. Chang, K.-F. Lin, C.-W. Wu, Y.-S. Chen, P.-F. Chiu, C.-C. Kuo, Y.-S. Yang, P.-C. Chiang, W.-P. Lin, C.-H. Lin, H.-Y. Lee, P.-Y. Gu, S.-M. Wang, F. T. Chen, K.-L. Su, C.-H. Lien, K.-H. Cheng, H.-T. Wu, T.-K. Ku, M.-J. Kao, and M.-J. Tsai, "4 Mb embedded SLC resistive-RAM macro with 7.2 ns read-write random-access time and 160 ns MLC-access capability," in Proc. IEEE Tech. Dig. ISSCC, 2011, pp. 200-202.
12. Y. S. Chen, H. Y. Lee, P. S. Chen, P. Y. Gu, C. W. Chen, W. P. Lin, W. H. Liu, Y. Y. Hsu, S. S. Sheu, P. C. Chiang, W. S. Chen, F. T. Chen, C. H. Lien, and M.-J. Tsai, "Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity," in IEEE Tech. Dig. IEDM, 2009, pp. 1-4.
13. S. C. Chae, J. S. Lee, S. Kim, S. B. Lee, S. H. Chang, C. Liu, B. Kahng, H. Shin, D.-W. Kim, C. U. Jung, S. Seo, M.-J. Lee, and T. W. Noh, "Random circuit breaker network model for unipolar resistance switching," Adv. Mater., vol. 20, no. 6, pp. 1154-1159, Mar. 2008.
14. X. Guan, S. Yu, and H.-S. P.Wong, "On the switching parameter variation of metal oxide RRAM-Part I: Physical modeling and simulation methodology," IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1172-1182, Apr. 2012.
15. S. Yu, Y. Wu, and H.-S. P. Wong, "Investigating the switching dynamics and multilevel capability of bipolar metal oxide resistive switching memory," Appl. Phys. Lett., vol. 98, no. 10, pp. 103 514-1-103 514-3, Mar. 2011.
16. S. Yu, Y.Wu, R. Jeyasingh, D. Kuzum, and H.-S. P.Wong, "An electronic synapse device based on metal oxide resistive switching memory for neuromorphic computation," IEEE Trans. Electron Devices, vol. 58, no. 8, pp. 2729-2737, Aug. 2011.
17. 2 \ Pt memory systems," Electrochem. Solid-State Lett., vol. 13, no. 6, pp. G54-G56, Apr. 2010.
18. 2 stack ReRAM for low-voltage and multilevel operation," IEEE Electron Device Lett., vol. 31, no. 3, pp. 204-206, Mar. 2010.
19. S. Yu, R. Jeyasingh, Y. Wu, and H.-S. P. Wong, "Understanding the conduction and switching mechanism of metal oxide RRAM through low frequency noise and AC conductance measurement and analysis," in IEDM Tech. Dig., 2011, pp. 12.1.1-12.1.4.
20. S. Yu and H.-S. P. Wong, "A phenomenological model for the reset mechanism of metal oxide RRAM," IEEE Electron Device Lett., vol. 31, no. 12, pp. 1455-1457, Dec. 2010.
21. 2 thin films with embedded Al layers," Electrochem. Solid-State Lett., vol. 13, no. 2, pp. H36-H38, 2010.
22. 2-based ReRAM with implanted Ti ions," IEEE Electron Device Lett., vol. 30, no. 12, pp. 1335-1337, Dec. 2009.
23. 2 thin films with embedded Pt nanocrystals," Appl. Phys. Lett., vol. 95, no. 4, pp. 042 104-1-042 104-3, Jul. 2009.
24. B. Lee and H.-S. P. Wong, "Fabrication and characterization of nanoscale NiO resistance change memory (RRAM) cells with confined conduction paths," IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3270-3275, Oct. 2011.
25. x crossbar resistive RAM with excellent performance, reliability and low-energy operation," in IEDM Tech. Dig., 2011, pp. 31.6.1-31.6.4.
26. M. Yin, P. Zhou, H. B. Lv, J. Xu, Y. L. Song, X. F. Fu, T. A. Tang, B. A. Chen, and Y. Y. Lin, "Improvement of resistive switching in CuxO using new RESET mode," IEEE Electron Device Lett., vol. 29, no. 7, pp. 681-683, Jul. 2008.
27. x bi-layer RRAM devices," in Symp. VLSI-TSA, 2011, pp. 1-2.
28. x switching dielectrics," IEEE Electron Device Lett., vol. 32, no. 9, pp. 1290-1292, Sep. 2011.
29. x bilayer structure on switching uniformity and reliability in nonvolatile memory applications," Appl. Phys. Lett., vol. 97, no. 17, pp. 172 105-1-172 105-3, Oct. 2010.
30. x based resistive switching memory," Appl. Phys. Lett., vol. 100, no. 4, pp. 043507-1-043507-4, Jan. 2012, to be published.