Efficiently enabling conventional block sizes for very large die-stacked DRAM caches

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 454-464

  Loh, Gabriel H ^a   Hill, Mark D ^b  

^a ADVANCED MICRO DEVICES   (United States)

^b University of Wisconsin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BLOCK SIZES; CACHE ORGANIZATION; COMMERCIAL WORKLOAD; DATA ACCESS; MAIN MEMORY; MULTI-CORE PROCESSOR; MULTIPLE LAYERS; OFF-CHIP; ON CHIPS; PERFORMANCE BENEFITS; TAG ARRAYS;

STATIC RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84858776535     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155673     Document Type: Conference Paper

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