Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architectures

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 2009, Pages 101-112

  Zhang, Wangyuan ^a   Li, Tao ^a  

^a University of Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D TECHNOLOGY; ANALYTICAL MODEL; BANDWIDTH CONSTRAINT; CHARGE LEAKAGE; CONVENTIONAL MEMORIES; ECC CODES; ELECTRICAL CHARACTERISTIC; HEAT-DRIVEN; HIGHER TEMPERATURES; LIFE SPAN; LOW POWER; MEMORY ARCHITECTURE; MEMORY LATENCIES; MEMORY SYSTEMS; ON-CHIP TEMPERATURE; OPTIMIZATION SCHEME; PAGE ALLOCATION; PERFORMANCE DEGRADATION; PHASE-CHANGE RANDOM ACCESS MEMORY; POWER CONSUMPTION; POWER DENSITIES; POWER OVERHEAD; POWER SAVINGS; PROGRAMMING CURRENTS; PROGRAMMING MECHANISM; STACKING TECHNOLOGY; THERMAL CONSTRAINTS; THREE DIMENSIONAL (3D) INTEGRATION; THROUGH SILICON VIAS;

COMPUTER CRIME; CONSTRAINED OPTIMIZATION; DIES; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC NETWORK ANALYSIS; FLASH MEMORY; PARALLEL ARCHITECTURES; PHASE CHANGE MEMORY; SIMULATORS;

THREE DIMENSIONAL;

EID: 70449623993     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.2009.30     Document Type: Conference Paper

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