Decoupled sectored caches: Conciliating low tag implementation cost and low miss ratio

Conference Proceedings - Annual International Symposium on Computer Architecture, ISCA

Volumn , Issue , 1994, Pages 384-393

  Seznec, Andre ^a  

^a CAMPUS DE BEAULIEU   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; CELLULAR ARRAYS; COMPUTER ARCHITECTURE; MICROPROCESSOR CHIPS; PRODUCT DESIGN; STORAGE ALLOCATION (COMPUTER); VIRTUAL STORAGE;

DECOUPLED SECTORED CACHES; LOW TAG IMPLEMENTATION COST; MISS RATIO;

DATA STORAGE EQUIPMENT;

EID: 0028324009     PISSN: 08847495     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)